公开(公告)号：US20110291261A1

公开(公告)日：2011-12-01

申请号：US12789316

申请日：2010-05-27

Applicant: Thomas J. Fleischman ,  Eric D. Perfecto ,  Sudipta K. Ray

Inventor： Thomas J. Fleischman ,  Eric D. Perfecto ,  Sudipta K. Ray

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/06181 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate. The plurality of primary electrically conductive pillars and associated connecting material provide a standoff height between the primary integrated circuit device and the substrate that is greater than or equal to a height of the one or more secondary integrated circuit devices.

Abstract translation: 公开了用于连接集成电路器件的装置，系统和方法。 多个初级导电触点和多个初级导电柱电耦合到初级集成电路器件。 多个初级导电触点形成对应于设置在一个或多个次级集成电路器件上的次级导电触点的图案。 多个主导电支柱远离主集成电路装置延伸。 多个主导电柱形成对应于设置在基板上的基板导电触点的图案。 多个初级导电柱和相关联的连接材料提供主集成电路器件和衬底之间的间隔高度，其大于或等于一个或多个次级集成电路器件的高度。

公开(公告)号：US07199450B2

公开(公告)日：2007-04-03

申请号：US10908480

申请日：2005-05-13

Applicant: Jon A. Casey ,  Michael Berger ,  Leena P. Buchwalter ,  Donald F. Canaperi ,  Raymond R. Horton ,  Anurag Jain ,  Eric D. Perfecto ,  James A. Tornello

Inventor： Jon A. Casey ,  Michael Berger ,  Leena P. Buchwalter ,  Donald F. Canaperi ,  Raymond R. Horton ,  Anurag Jain ,  Eric D. Perfecto ,  James A. Tornello

IPC: H01L29/06 ,  H01L23/58

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Abstract translation: 使用无粘性，低粘度，高温稳定的聚合物或低粘度的高固含量聚合物溶液密封通孔，其中聚合物材料在高温下浸渍在通孔内。 引入供应室以在升高的温度下施用聚合物材料，通常在高至足以液化聚合物材料的温度下。 聚合物材料通过来自泵，活塞或保持在所述供应室内的真空的力的加热供应管线引入。

公开(公告)号：US06638374B2

公开(公告)日：2003-10-28

申请号：US10050285

申请日：2002-01-16

Applicant: Patrick W. DeHaven ,  Charles C. Goldsmith ,  Jeffery L. Hurd ,  Suryanarayana Kaja ,  Michele S. Legere ,  Eric D. Perfecto

Inventor： Patrick W. DeHaven ,  Charles C. Goldsmith ,  Jeffery L. Hurd ,  Suryanarayana Kaja ,  Michele S. Legere ,  Eric D. Perfecto

IPC: B32B1502

CPC classification number: C25D5/50 ,  H05K1/09 ,  H05K3/22 ,  H05K2203/0723 ,  H05K2203/1105 ,  Y10T428/12431 ,  Y10T428/12882 ,  Y10T428/12903

Abstract: A process for controlling grain growth in the microstructure of thin metal films (e.g., copper or gold) deposited onto a substrate. In one embodiment, the metal film is deposited onto the substrate to form a film having a fine-grained microstructure. The film is heated in a temperature range of 70-100° C. for at least five minutes, wherein the fine-grained microstructure is converted into a stable large-grained microstructure. In another embodiment, the plated film is stored, after the step of depositing, at a temperature not greater than −20° C., wherein the fine-grained microstructure is stabilized without grain growth for the entire storage period.

公开(公告)号：US6126761A

公开(公告)日：2000-10-03

申请号：US95253

申请日：1998-06-10

Applicant: Patrick W. DeHaven ,  Charles C. Goldsmith ,  Jeffrey L. Hurd, deceased ,  Suryanarayana Kaja ,  Michele S. Legere ,  Eric D. Perfecto

Inventor： Patrick W. DeHaven ,  Charles C. Goldsmith ,  Jeffrey L. Hurd, deceased ,  Suryanarayana Kaja ,  Michele S. Legere ,  Eric D. Perfecto

IPC: H01L21/28 ,  C25D5/50 ,  C25D7/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/52 ,  H05K1/09 ,  H05K3/22

CPC classification number: C25D5/50 ,  H05K3/22 ,  H05K1/09 ,  H05K2203/0723 ,  H05K2203/1105 ,  Y10T428/12431 ,  Y10T428/12882 ,  Y10T428/12903

Abstract: A process for controlling grain growth in the microstructure of thin metal films (e.g., copper or gold) deposited onto a substrate. In one embodiment, the metal film is deposited onto the substrate to form a film having a fine-grained microstructure. The film is heated in a temperature range of 70-100.degree. C. for at least five minutes, wherein the fine-grained microstructure is converted into a stable large-grained microstructure. In another embodiment, the plated film is stored, after the step of depositing, at a temperature not greater than -20.degree. C., wherein the fine-grained microstructure is stabilized without grain growth for the entire storage period.

Abstract translation: 控制沉积在基底上的薄金属薄膜（例如铜或金）的微结构中的晶粒生长的方法。 在一个实施方案中，将金属膜沉积到基底上以形成具有细晶粒微结构的膜。 将膜在70-100℃的温度范围内加热至少5分钟，其中细晶粒微结构转化为稳定的大粒度微观结构。 在另一个实施方案中，在沉积步骤之后，在不大于-20℃的温度下储存镀膜，其中在整个保存期间细晶粒微结构稳定而没有晶粒生长。

公开(公告)号：US5534466A

公开(公告)日：1996-07-09

申请号：US457191

申请日：1995-06-01

Applicant: Eric D. Perfecto ,  Chandrika Prasad ,  George E. White ,  Kwong H. Wong

Inventor： Eric D. Perfecto ,  Chandrika Prasad ,  George E. White ,  Kwong H. Wong

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/68 ,  H01L23/538 ,  H05K3/20 ,  H05K3/28 ,  H05K3/46 ,  H01L21/18

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/5385 ,  H05K3/205 ,  H05K3/4614 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K3/28 ,  H05K3/4623 ,  H05K3/467 ,  Y10T156/1052

Abstract: A process for transferring a thin film wiring layer to a substrate in the construction of multilayer chip modules initially provides a sacrificial release layer formed on a surface of a carrier. Directly on the release layer there is formed in inverted fashion a plurality of multilevel thin film structures having at least one wiring path of metallic material exposed on the surface opposite the carrier. An electronic packaging substrate is provided, and solder or other joining material is applied to one or both of the exposed metallic surface of the multilevel thin film structure or the substrate. The multilevel thin film structure is then joined to the substrate so that the attached carrier is remote from the substrate. The release layer is subsequently contacted with an etchant for the release layer so as to remove the carrier from the multilevel thin film structure to produce a multilayer chip module.

Abstract translation: 在多层芯片模块的结构中将薄膜布线层转移到基板的工艺最初提供了形成在载体表面上的牺牲脱离层。 直接在释放层上形成多个多层薄膜结构，其具有在与载体相对的表面上暴露的金属材料的至少一个布线路径。 提供电子封装基板，并且将焊料或其它接合材料施加到多层薄膜结构或基板的暴露的金属表面中的一个或两个。 然后将多层薄膜结构连接到基板，使得附着的载体远离基板。 随后将释放层与用于剥离层的蚀刻剂接触，以便从多层薄膜结构中除去载体以产生多层芯片模块。