公开(公告)号：US5554555A

公开(公告)日：1996-09-10

申请号：US353897

申请日：1994-12-12

申请人： Michael D. Rostoker ,  Nicholas F. Pasch

发明人： Michael D. Rostoker ,  Nicholas F. Pasch

IPC分类号： H01L21/266 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/00

CPC分类号： H01L21/31051 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/823871 ,  Y10S438/981

摘要： Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into, the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

摘要翻译： 公开了基于下面的MOS结构在半导体器件中平面化具有不规则顶表面拓扑的一个或多个层的方法。 还公开了为底层MOS结构产生掺杂阱或区域的方法，其中在衬底的表面上使用厚的氧化物生长来掩蔽离子注入到阱中。 还公开了一种用于产生一对相邻的互补相对掺杂阱的技术，例如使用厚氧化物生长作为掩模的CMOS结构。 对一个或多个层进行平坦化的方法之一包括在拓扑层顶部沉积，致密化和再流动玻璃层。 平面化一个或多个层的另一种方法包括沉积，致密化和化学机械抛光沉积的和致密化的玻璃，从而避免对底层扩散产生不利影响的附加温度循环（即，用于重新流动玻璃）。

公开(公告)号：US5539174A

公开(公告)日：1996-07-23

申请号：US249398

申请日：1994-05-26

申请人： Michael D. Rostoker ,  Nicholas F. Pasch

发明人： Michael D. Rostoker ,  Nicholas F. Pasch

IPC分类号： H01L21/768 ,  H05K3/02 ,  B23K26/16

CPC分类号： H01L21/76894 ,  H05K3/027 ,  Y10T29/49156

摘要： A laser is used to cut or "zap" unwanted sections of an aluminum interconnect metallization pattern on a microelectronic circuit substrate. Vaporized aluminum forms a cloud above the substrate that is reacted with a gas to form a substance which can be prevented from solidifying and forming a conductive residue on the substrate that could create a short circuit in the metallization pattern. The gas can be pressurized oxygen, in which case the reactant substance is electrically insulative aluminum oxide that forms a desirable sealing coating over the cut area. The aluminum oxide has a lower density than aluminum, and expands in the cut area to form a hermetic seal with the facing edges of the metallization pattern. Alternatively, the gas can be chlorine or other material which forms a residue that can be easily removed using a solvent such as water.

摘要翻译： 激光用于在微电子电路基板上切割或“切割”铝互连金属化图案的不想要的部分。 蒸发的铝在基板上形成与气体反应的云，以形成可以防止在基板上固化和形成可能在金属化图案中短路的导电残留物的物质。 气体可以是加压氧气，在这种情况下，反应物质是电绝缘氧化铝，在切割区域上形成期望的密封涂层。 氧化铝具有比铝低的密度，并且在切割区域中膨胀以与金属化图案的相对边缘形成气密密封。 或者，气体可以是氯或其它形成残留物的材料，其可以使用诸如水的溶剂容易地除去。

公开(公告)号：US5532934A

公开(公告)日：1996-07-02

申请号：US416457

申请日：1995-04-03

申请人： Michael D. Rostoker

发明人： Michael D. Rostoker

IPC分类号： G03F7/20 ,  G06F17/50 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495 ,  H01L27/02 ,  H01L29/06 ,  H01L23/50

CPC分类号： H01L24/06 ,  G03F7/70433 ,  G06F17/5072 ,  H01L23/315 ,  H01L23/49503 ,  H01L23/49558 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/4912 ,  H01L24/49 ,  H01L29/0657 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10155 ,  H01L2924/14

摘要： A technique for integrated circuit floorplanning using irregularly shaped dies (e.g., triangular, elongated rectangular, parallelogram-shaped, etc.) is described whereby the layout of the integrated circuit die is accomplished by partitioning (slicing) the die into progressively smaller groups of more than two areas into which functions (active elements, or circuits) are assigned according to their area requirements. The die is iteratively sub-partitioned.

摘要翻译： 描述了使用不规则形状的模具（例如，三角形，细长的矩形，平行四边形形状等）的集成电路布图规划的技术，由此通过将模具分成（切片）成逐渐变小的更多的组来实现集成电路管芯的布局 功能（有源元件或电路）根据其面积要求分配的两个区域。 模具被迭代地子分区。

公开(公告)号：US5521108A

公开(公告)日：1996-05-28

申请号：US121679

申请日：1993-09-15

申请人： Michael D. Rostoker ,  Ashok Kapoor

发明人： Michael D. Rostoker ,  Ashok Kapoor

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L21/2807 ,  H01L27/11517 ,  H01L29/42324 ,  Y10S148/059

摘要： A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the roughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed. A further oxide layer may then be formed over the second conductive layer followed by a patterning step to respectively form the floating gate (from the germanium/silicon layer) and the control gate from the second conductive layer.

摘要翻译： 描述了导电构件，其上具有受控粗糙度的表面，其可用于集成电路结构的构造。 在优选实施例中，使用锗和硅的混合物形成导电构件，然后将其氧化，导致在锗/硅导电构件上形成粗糙表面，这是由于锗的氧化速率的差异 和硅。 在氧化导电部件之后，可以去除氧化物层，使锗/硅导电部件上的粗糙表面残留。 当使用具有粗糙表面的导电部件形成诸如EPROM的集成电路结构时，然后在粗糙表面上沉积另外的氧化物层，随后沉积第二层导电材料，例如多晶硅或锗 /硅混合物，从其形成控制栅极。 然后可以在第二导电层上形成另外的氧化物层，接着形成图案化步骤以分别从第二导电层形成浮栅（来自锗/硅层）和控制栅极。

公开(公告)号：US5504035A

公开(公告)日：1996-04-02

申请号：US105547

申请日：1993-08-12

申请人： Michael D. Rostoker ,  Nicholas F. Pasch

发明人： Michael D. Rostoker ,  Nicholas F. Pasch

IPC分类号： G03F7/20 ,  H01L21/56 ,  H01L21/60 ,  H01L31/0232 ,  H05K3/30 ,  H05K3/34 ,  H01L21/283 ,  H01L21/58

CPC分类号： G03F7/70433 ,  H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L31/0232 ,  H05K3/3436 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K2201/10424 ,  H05K2203/167 ,  H05K3/303 ,  H05K3/3431 ,  H05K3/3489 ,  Y02P70/613

摘要： A process of interconnecting a semiconductor device to a substrate wherein solder balls on the semiconductor device are fused with one side of an embedded noble metal foil within a through hole in an interposer structure. Solder balls on the substrate are fused with the metal foil within the structure window on the other side of the metal foil.

摘要翻译： 将半导体器件与衬底互连的工艺，其中半导体器件上的焊球与插入式结构中的通孔内的嵌入的贵金属箔的一侧熔合。 基板上的焊球与金属箔的另一侧的结构窗内的金属箔熔合。

公开(公告)号：US5489538A

公开(公告)日：1996-02-06

申请号：US370565

申请日：1995-01-09

申请人： Michael D. Rostoker ,  Conrad Dell'Oca

发明人： Michael D. Rostoker ,  Conrad Dell'Oca

IPC分类号： G01R31/28 ,  G01R31/26 ,  H01L21/66

CPC分类号： G01R31/2863 ,  G01R31/2856 ,  Y10S148/162

摘要： The present invention provides for a burn-in test which is conducted on the wafer level, before the dies are separated into individual chips and packaged. In a preferred embodiment of the invention, a series of chips are each connected to an external current, ground, and/or alternate signal source(s) for burn-in. Generally, the method herein for a burn-in of a semiconductor die comprises the step of: (a) providing an electrical connection between a die on a semiconductor wafer and an external current source; (b) heating the semiconductor wafer; and (c) applying a common signal across the electrical connection to burn in the die. A preferred method herein provides a semiconductor wafer including a multiplicity of dies and wafer level test points, at least one layer of conductive lines overlying the semiconductor wafer, a means for connecting an individual conductive line to a test point on the wafer; and a means for connecting the conductive lines to an external signal source for exercising the dies.

摘要翻译： 本发明提供一种在晶片级别上进行的老化测试，在芯片被分离成单个芯片并被封装之前。 在本发明的优选实施例中，一系列芯片各自连接到用于老化的外部电流，接地和/或交替信号源。 通常，本文中用于半导体管芯的老化的方法包括以下步骤：（a）在半导体晶片上的管芯和外部电流源之间提供电连接; （b）加热半导体晶片; 并且（c）在电连接上施加公共信号以在模具中燃烧。 本文优选的方法提供了包括多个管芯和晶片级测试点的半导体晶片，覆盖半导体晶片的至少一层导电线，用于将单个导线连接到晶片上的测试点的装置; 以及用于将导线连接到用于锻模的外部信号源的装置。

公开(公告)号：US5374974A

公开(公告)日：1994-12-20

申请号：US56239

申请日：1993-04-30

申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

IPC分类号： G02B17/00 ,  G02B26/02 ,  G02B27/09 ,  G02F1/19 ,  G02F1/33 ,  G03F7/20 ,  G21K1/04 ,  G03B27/72 ,  G02F1/00

CPC分类号： G02B27/0994 ,  G02B17/00 ,  G02B26/02 ,  G02F1/19 ,  G03F7/70008 ,  G03F7/702 ,  G03F7/70375 ,  G21K1/04 ,  G02F1/33 ,  Y10S430/107 ,  Y10S430/108

摘要： Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A continuous stream of such radiation is gated on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The distortable-surface device is a surface acoustic wave device, a magnetostrictive device, or the like. The beam-blocking device is a beam stop, such as a knife edge, an aperture, or the like. The distortable-surface device can be selectively caused to reflect an incident beam of radiation past or into the beam-blocking device. In this manner, a continuous stream of radiation, such as from a pellet of Cobalt-60, can be quickly and precisely gated on and off to impact and to not-impact the semiconductor wafer, respectively. By moving either of the reflected beam or the semiconductor wafer, line features can be created in the sensitized layer on the semiconductor wafer.

摘要翻译： 通过诸如X射线或γ射线的低波长辐射束在半导体晶片上的敏化层中产生细微亚微米线特征和图案。 这种辐射的连续流由包括可变形表面装置和束阻挡装置的快门机构开启和关闭。 可变形表面装置是表面声波装置，磁致伸缩装置等。 光束阻挡装置是光束挡块，例如刀刃，孔等。 可变形表面装置可以选择性地反射入射束阻挡装置的入射入射光束。 以这种方式，连续的辐射流，例如来自Cobalt-60的颗粒，可以快速且精确地选通开启和关闭以冲击并且不影响半导体晶片。 通过移动反射光束或半导体晶片中的任何一个，可以在半导体晶片上的增感层中产生线特征。

公开(公告)号：US5340978A

公开(公告)日：1994-08-23

申请号：US51028

申请日：1993-04-21

申请人： Michael D. Rostoker ,  David E. Sanders

发明人： Michael D. Rostoker ,  David E. Sanders

IPC分类号： G02F1/13 ,  H01L27/146 ,  H04N5/225 ,  H04N5/335 ,  H01J40/14

CPC分类号： H01L27/14625 ,  H01L27/14645 ,  H04N5/2254 ,  H04N5/335

摘要： A camera comprising various arrangements for employing optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements and methods of making same are discussed.

摘要翻译： 描述了包括与光敏元件相关联的用于采用光学元件的各种布置的照相机。 在一些布置中，光学元件与包含感光元件的基板一体地形成。 在其他布置中，将光学元件安装到包含基板和感光元件的封装等上。 在其他布置中，采用两个或多个光学元件，包括常规折射元件，折射聚焦元件和折射光束分离元件。 讨论了作为固态图像传感器的实用性。 讨论了单色和彩色成像的实用性。 讨论了基于这种相机布置的各种装置及其制造方法。

公开(公告)号：US06754196B1

公开(公告)日：2004-06-22

申请号：US09063476

申请日：1998-04-20

申请人： John Daane ,  Michael D. Rostoker ,  Sandeep Jaggi

发明人： John Daane ,  Michael D. Rostoker ,  Sandeep Jaggi

IPC分类号： H04Q724

CPC分类号： H04W72/0453

摘要： A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.

摘要翻译： 多个设备通过无线电频率的无线网络传送信息。 信息包括数字音频，视频和数据。 动态分配设备之间的带宽，根据设备的需要进行分配。 无线网络的一个实施例是时分多址网络。 另一个实施例是无线以太网。 另一个实施例是频分复用网络。

公开(公告)号：US06418353B1

公开(公告)日：2002-07-09

申请号：US09064802

申请日：1998-04-22

申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

IPC分类号： G06F1900

CPC分类号： G03F7/705 ,  G03F7/70433 ,  G03F7/70625

摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 制造数据包括流程和。 然后将产量参数转移回瑞利处理器用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。