公开(公告)号：US07515435B2

公开(公告)日：2009-04-07

申请号：US11646339

申请日：2006-12-28

Applicant: Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC: H05K1/16

CPC classification number: H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract translation: 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US20070168148A1

公开(公告)日：2007-07-19

申请号：US11591381

申请日：2006-11-01

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: G06F19/00 ,  G01R31/00

CPC classification number: G01R31/2818 ,  G01R31/2805 ,  G01R31/304

Abstract: A test method of an embedded capacitor and test system thereof are provided. The method and system are used to determine an electrical specification of the embedded capacitive component in a circuit board substrate, thereby avoiding executing a follow-up fabricating process for the circuit board substrate not satisfying the desired specification. In the method and system, a geometric size of the embedded capacitor is measured, and a relation value between the electrical parameter and the geometric size and a standard electrical parameter are obtained from a model database, to calculate the electrical parameter of the embedded capacitor. Then, the electrical parameter of the embedded capacitor is compared with the standard electrical parameter, to obtain an error value. Therefore, according to the error value, it may be acquired whether or not the circuit board substrate satisfies set electrical specifications.

Abstract translation: 提供了一种嵌入式电容器及其测试系统的测试方法。 该方法和系统用于确定电路板基板中的嵌入式电容元件的电气规格，从而避免执行不满足期望规格的电路板基板的后续制造工艺。 在该方法和系统中，测量嵌入式电容器的几何尺寸，并从模型数据库中获得电参数和几何尺寸之间的关系值以及标准电参数，以计算嵌入式电容器的电参数。 然后，将嵌入式电容器的电气参数与标准电气参数进行比较，以获得误差值。 因此，根据误差值，可以获取电路板基板是否满足设定的电气规格。

公开(公告)号：US20070164395A1

公开(公告)日：2007-07-19

申请号：US11308493

申请日：2006-03-30

Applicant: Jiin-Shing Perng ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

Inventor： Jiin-Shing Perng ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC: H01L29/00

CPC classification number: H01L23/642 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49589 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A chip package with built-in capacitor structure including an integrated circuit (IC) unit, a capacitor unit, a carrier and a molding compound is provided. The capacitor unit is disposed on the IC unit and includes a first metal foil, a second metal foil, and a dielectric layer disposed between the first metal foil and the second metal foil. The carrier is disposed on the surface away from the dielectric layer of the second metal foil. The first metal foil is electrically connected to the carrier, the second metal foil is electrically connected to the carrier, the IC unit is electrically connected to the carrier, the IC unit is electrically connected to the first metal foil, and the IC unit is electrically connected to the second metal foil. The molding compound is disposed on the carrier for fixing the IC unit, the capacitor unit and the carrier.

Abstract translation: 提供具有集成电路（IC）单元，电容器单元，载体和模塑料的内置电容器结构的芯片封装。 电容器单元设置在IC单元上，并且包括第一金属箔，第二金属箔和设置在第一金属箔和第二金属箔之间的电介质层。 载体设置在远离第二金属箔的电介质层的表面上。 第一金属箔与载体电连接，第二金属箔电连接到载体上，IC单元与载体电连接，IC单元电连接到第一金属箔，并且IC单元电气 连接到第二金属箔。 模制化合物设置在载体上用于固定IC单元，电容器单元和载体。

公开(公告)号：US20060285273A1

公开(公告)日：2006-12-21

申请号：US11156350

申请日：2005-06-17

Applicant: Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

Inventor： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC: H01G4/20

CPC classification number: H05K1/024 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P3/081 ,  H01P3/085 ,  H05K1/0298 ,  H05K3/386 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09881 ,  H01L2924/00

Abstract: This invention discloses a composite distributed dielectric structure. It comprises one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein, respectively described in two embodiments. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers The invention provides a low cost and practical dielectric structure for interconnect systems to reduce dielectric loss, cross talk, and signal propagation delay and to well control the impedance matching while maintaining proper heat dissipation and noise reduction at high frequency transmission.

Abstract translation: 本发明公开了一种复合分布介质结构。 它包括一个或多个导体层，分布在导体层上的一个或多个电介质层，以及分布在电介质层上的一个或多个导体迹线。 一个或多个电介质板可以进一步围绕导体迹线。 在两个实施例中分别描述了介电层或板可以具有或可以不具有多个电介质材料。 每个导体迹线位于介电材料上，而不会穿过两种不同的介电材料。 两个或多个电介质层可以堆叠在导体层上本发明为互连系统提供了一种低成本和实用的电介质结构，以减少介质损耗，串扰和信号传播延迟，并且在保持适当的散热的同时良好地控制阻抗匹配， 高频传输降噪。

公开(公告)号：US20060261482A1

公开(公告)日：2006-11-23

申请号：US11131741

申请日：2005-05-18

Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC: H01L23/52

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167

Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

Abstract translation: 一种多层电路板，包括多个端子的内置组件，至少一个形成在用于信号传输的多层电路板的顶表面上的信号焊盘，所述至少一个信号焊盘中的每一个对应于多个 端子和形成在多层电路板的顶表面上的至少一个测试焊盘，所述至少一个测试焊盘中的每一个对应于至少一个信号焊盘中的一个，用于测试从一个信号焊盘延伸的电路径 通过所述一个端子到所述至少一个测试垫中的每一个。

公开(公告)号：US06683781B2

公开(公告)日：2004-01-27

申请号：US10152669

申请日：2002-05-23

Applicant: Ted C. Ho ,  Min-Lin Lee ,  Huey-Ru Chang ,  Shinn-Juh Lay

Inventor： Ted C. Ho ,  Min-Lin Lee ,  Huey-Ru Chang ,  Shinn-Juh Lay

IPC: H01G400

CPC classification number: H01L23/642 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A packaging structure with low switching noises is disclosed. In this structure, a chip capacitor is connected to a chip. The chip capacitor is a capacitor structure formed using a high dielectric material to provide a better noise filtering effect. Therefore, the invention can effectively lower switching noises.

Abstract translation: 公开了一种具有低开关噪声的封装结构。 在该结构中，芯片电容器连接到芯片。 片式电容器是使用高介电材料形成的电容器结构，以提供更好的噪声滤波效果。 因此，本发明可以有效地降低开关噪声。

公开(公告)号：US06683469B2

公开(公告)日：2004-01-27

申请号：US09858538

申请日：2001-05-17

Applicant: Min-Lin Lee ,  Chin-Sun Shyu

Inventor： Min-Lin Lee ,  Chin-Sun Shyu

IPC: G01R3102

CPC classification number: G01R31/318572 ,  G01R29/26

Abstract: A regulable test IC system for signal noise on the electrical analysis point, comprising: a power supply, for providing a test voltage in the system; a pulse generator, for providing a test frequency in a noise testing of the system; a regulable test IC with different signal pads capable of regulable testing signal noise with the test frequency from the pulse generator and the test voltage from the power supply in a plurality of built-in specific structures, under the basis of an assigned current standard; and a digital detection device with a display, for displaying and recording the result of the regulable test.

Abstract translation: 一种用于电气分析点上的信号噪声的可调节测试IC系统，包括：用于在系统中提供测试电压的电源; 脉冲发生器，用于在系统的噪声测试中提供测试频率; 具有不同信号焊盘的可调节测试IC，其具有在分配的当前标准的基础上具有来自脉冲发生器的测试频率的可调节测试信号噪声和来自多个内置特定结构中的电源的测试电压; 以及具有显示器的数字检测装置，用于显示和记录可调节测试的结果。

公开(公告)号：US08237520B2

公开(公告)日：2012-08-07

申请号：US12395065

申请日：2009-02-27

Applicant: Huey-Ru Chang ,  Min-Lin Lee ,  Jiin-Shing Perng ,  Sheng-Che Hung ,  Shinn-Juh Lai

Inventor： Huey-Ru Chang ,  Min-Lin Lee ,  Jiin-Shing Perng ,  Sheng-Che Hung ,  Shinn-Juh Lai

IPC: H03H7/00

CPC classification number: H03H1/02 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/1006

Abstract: A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency.

Abstract translation: 提供电容器装置。 电容器装置包括至少一个电容器。 电容器装置还包括第一电容器和耦合第一电容器和导电区域的第一滤波器，其中第一电容器具有第一谐振频率，并且第一滤波器被配置为在覆盖第一谐振频率的第一频带上操作。

公开(公告)号：US08227894B2

公开(公告)日：2012-07-24

申请号：US12410466

申请日：2009-03-25

Applicant: Min-Lin Lee ,  Shih-Hsien Wu ,  Shinn-Juh Lai ,  Shur-Fen Liu

Inventor： Min-Lin Lee ,  Shih-Hsien Wu ,  Shinn-Juh Lai ,  Shur-Fen Liu

IPC: H01L29/423

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/232 ,  H01L23/50 ,  H01L23/642 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/3011

Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.

Abstract translation: 逐步电容器结构包括至少一个逐步导电层。 逐步电容器表示多个电容器的特征。 当电流流过逐级电容器时，响应于不同的电流频率，在逐层电容器的上导体和底导体之间存在不同的电流路径; 在每个路径中感应不同的电感器，并通过如本文所公开的逐步电容器结构去耦合。

公开(公告)号：US08179695B2

公开(公告)日：2012-05-15

申请号：US12783478

申请日：2010-05-19

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: H05K9/00

CPC classification number: H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract translation: 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。