公开(公告)号：US07893359B2

公开(公告)日：2011-02-22

申请号：US11470435

申请日：2006-09-06

申请人： Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chih-Hao Chang

发明人： Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chih-Hao Chang

IPC分类号： H05K1/16 ,  H05K1/18

CPC分类号： H05K1/162 ,  H05K3/4611 ,  H05K2201/0209 ,  H05K2201/09309 ,  Y10T29/43 ,  Y10T29/49126

摘要： An embedded capacitor core including a first set of capacitors, a second set of capacitors, and an inter-layer dielectric film between the first set of capacitors and the second set of capacitors. The first set of capacitors includes: a first conductive pattern comprising at least two conductive electrodes; a second conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the first conductive pattern; and a first dielectric film between the first conductive pattern and the second conductive pattern. The second set of capacitors includes: a third conductive pattern comprising at least two conductive electrodes; a fourth conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the third conductive pattern; and a second dielectric film between the third conductive pattern and the fourth conductive pattern.

摘要翻译： 一种嵌入式电容器芯，包括第一组电容器，第二组电容器和在第一组电容器和第二组电容器之间的层间电介质膜。 第一组电容器包括：包括至少两个导电电极的第一导电图案; 第二导电图案，包括对应于第一导电图案的两个导电电极的至少两个导电电极; 以及在第一导电图案和第二导电图案之间的第一电介质膜。 第二组电容器包括：包括至少两个导电电极的第三导电图案; 第四导电图案，包括对应于第三导电图案的两个导电电极的至少两个导电电极; 以及在第三导电图案和第四导电图案之间的第二电介质膜。

公开(公告)号：US20060285273A1

公开(公告)日：2006-12-21

申请号：US11156350

申请日：2005-06-17

申请人： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

发明人： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC分类号： H01G4/20

CPC分类号： H05K1/024 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P3/081 ,  H01P3/085 ,  H05K1/0298 ,  H05K3/386 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09881 ,  H01L2924/00

摘要： This invention discloses a composite distributed dielectric structure. It comprises one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein, respectively described in two embodiments. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers The invention provides a low cost and practical dielectric structure for interconnect systems to reduce dielectric loss, cross talk, and signal propagation delay and to well control the impedance matching while maintaining proper heat dissipation and noise reduction at high frequency transmission.

摘要翻译： 本发明公开了一种复合分布介质结构。 它包括一个或多个导体层，分布在导体层上的一个或多个电介质层，以及分布在电介质层上的一个或多个导体迹线。 一个或多个电介质板可以进一步围绕导体迹线。 在两个实施例中分别描述了介电层或板可以具有或可以不具有多个电介质材料。 每个导体迹线位于介电材料上，而不会穿过两种不同的介电材料。 两个或多个电介质层可以堆叠在导体层上本发明为互连系统提供了一种低成本和实用的电介质结构，以减少介质损耗，串扰和信号传播延迟，并且在保持适当的散热的同时良好地控制阻抗匹配， 高频传输降噪。

公开(公告)号：US07349196B2

公开(公告)日：2008-03-25

申请号：US11156350

申请日：2005-06-17

申请人： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

发明人： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC分类号： H01G4/06

CPC分类号： H05K1/024 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P3/081 ,  H01P3/085 ,  H05K1/0298 ,  H05K3/386 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09881 ,  H01L2924/00

摘要： A composite distributed dielectric structure includes one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further formed around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers.

摘要翻译： 复合分布介质结构包括一个或多个导体层，分布在导体层上的一个或多个电介质层和分布在电介质层上的一个或多个导体迹线。 可以在导体迹线周围进一步形成一个或多个电介质板。 介电层或板可以具有或可以不具有多个电介质材料。 每个导体迹线位于介电材料上，而不会穿过两种不同的介电材料。 可以在导体层上堆叠两个或更多个电介质层。

公开(公告)号：US20070164395A1

公开(公告)日：2007-07-19

申请号：US11308493

申请日：2006-03-30

申请人： Jiin-Shing Perng ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

发明人： Jiin-Shing Perng ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC分类号： H01L29/00

CPC分类号： H01L23/642 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49589 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip package with built-in capacitor structure including an integrated circuit (IC) unit, a capacitor unit, a carrier and a molding compound is provided. The capacitor unit is disposed on the IC unit and includes a first metal foil, a second metal foil, and a dielectric layer disposed between the first metal foil and the second metal foil. The carrier is disposed on the surface away from the dielectric layer of the second metal foil. The first metal foil is electrically connected to the carrier, the second metal foil is electrically connected to the carrier, the IC unit is electrically connected to the carrier, the IC unit is electrically connected to the first metal foil, and the IC unit is electrically connected to the second metal foil. The molding compound is disposed on the carrier for fixing the IC unit, the capacitor unit and the carrier.

摘要翻译： 提供具有集成电路（IC）单元，电容器单元，载体和模塑料的内置电容器结构的芯片封装。 电容器单元设置在IC单元上，并且包括第一金属箔，第二金属箔和设置在第一金属箔和第二金属箔之间的电介质层。 载体设置在远离第二金属箔的电介质层的表面上。 第一金属箔与载体电连接，第二金属箔电连接到载体上，IC单元与载体电连接，IC单元电连接到第一金属箔，并且IC单元电气 连接到第二金属箔。 模制化合物设置在载体上用于固定IC单元，电容器单元和载体。

公开(公告)号：US07875808B2

公开(公告)日：2011-01-25

申请号：US11531337

申请日：2006-09-13

申请人： Huey-Ru Chang ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin Sun Shyu

发明人： Huey-Ru Chang ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin Sun Shyu

IPC分类号： H05K1/16

CPC分类号： H01L23/50 ,  H01G4/38 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/01079 ,  H05K1/0231 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/10734

摘要： An embedded capacitor device within a circuit board having an integrated circuitry thereon is provided. The circuit board has a common coupling area under the integrated circuitry. The embedded capacitor device includes a first capacitor section providing at least one capacitor to a first terminal set of the integrated circuitry and a second capacitor section providing at least one capacitor to a second terminal set of the integrated circuitry. A portion of the first capacitor section is in the common coupling area and has its coupling to the first terminal set located in the common coupling area. Similarly, a portion of the second capacitor section is in the common coupling area and has its coupling to the second terminal set located in the common coupling area.

摘要翻译： 提供了具有集成电路的电路板内的嵌入式电容器件。 电路板在集成电路下具有公共耦合区域。 嵌入式电容器装置包括：向集成电路的第一端子组提供至少一个电容器的第一电容器部分和向集成电路的第二端子组提供至少一个电容器的第二电容器部分。 第一电容器部分的一部分在公共耦合区域中，并且其耦合到位于公共耦合区域中的第一端子组。 类似地，第二电容器部分的一部分在公共耦合区域中，并且其耦合到位于公共耦合区域中的第二端子组。

公开(公告)号：US07515435B2

公开(公告)日：2009-04-07

申请号：US11646339

申请日：2006-12-28

申请人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC分类号： H05K1/16

CPC分类号： H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US20060261482A1

公开(公告)日：2006-11-23

申请号：US11131741

申请日：2005-05-18

申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC分类号： H01L23/52

CPC分类号： H05K1/0268 ,  G01R31/2818 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167

摘要： A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

摘要翻译： 一种多层电路板，包括多个端子的内置组件，至少一个形成在用于信号传输的多层电路板的顶表面上的信号焊盘，所述至少一个信号焊盘中的每一个对应于多个 端子和形成在多层电路板的顶表面上的至少一个测试焊盘，所述至少一个测试焊盘中的每一个对应于至少一个信号焊盘中的一个，用于测试从一个信号焊盘延伸的电路径 通过所述一个端子到所述至少一个测试垫中的每一个。

公开(公告)号：US06683781B2

公开(公告)日：2004-01-27

申请号：US10152669

申请日：2002-05-23

申请人： Ted C. Ho ,  Min-Lin Lee ,  Huey-Ru Chang ,  Shinn-Juh Lay

发明人： Ted C. Ho ,  Min-Lin Lee ,  Huey-Ru Chang ,  Shinn-Juh Lay

IPC分类号： H01G400

CPC分类号： H01L23/642 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A packaging structure with low switching noises is disclosed. In this structure, a chip capacitor is connected to a chip. The chip capacitor is a capacitor structure formed using a high dielectric material to provide a better noise filtering effect. Therefore, the invention can effectively lower switching noises.

摘要翻译： 公开了一种具有低开关噪声的封装结构。 在该结构中，芯片电容器连接到芯片。 片式电容器是使用高介电材料形成的电容器结构，以提供更好的噪声滤波效果。 因此，本发明可以有效地降低开关噪声。

公开(公告)号：US08035036B2

公开(公告)日：2011-10-11

申请号：US11861297

申请日：2007-09-26

申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC分类号： H05K1/16

CPC分类号： H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

摘要： A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

摘要翻译： 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。

公开(公告)号：US20070164396A1

公开(公告)日：2007-07-19

申请号：US11646339

申请日：2006-12-28

申请人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC分类号： H01L29/00

CPC分类号： H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。