公开(公告)号：US12096636B2

公开(公告)日：2024-09-17

申请号：US17479573

申请日：2021-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Fei Zhou

IPC: H10B43/35 ,  G11C7/18 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C7/18 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

公开(公告)号：US12094944B2

公开(公告)日：2024-09-17

申请号：US17316015

申请日：2021-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dai Iwata ,  Hiroshi Nakatsuji ,  Hiroyuki Ogawa ,  Eiichi Fujikura

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/07 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42356 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6656

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

公开(公告)号：US12079496B2

公开(公告)日：2024-09-03

申请号：US17901310

申请日：2022-09-01

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Xiang Yang

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.

公开(公告)号：US12061805B2

公开(公告)日：2024-08-13

申请号：US17483470

申请日：2021-09-23

Applicant: SanDisk Technologies LLC

Inventor： Reuven Elhamias ,  Ram Fishler

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1028 ,  Y02D10/00

Abstract: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

公开(公告)号：US12058854B2

公开(公告)日：2024-08-06

申请号：US17232209

申请日：2021-04-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Akio Nishida ,  Masanori Tsutsumi

IPC: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory die includes source-select-level electrically conductive strips laterally spaced apart by source-select-level dielectric isolation structures, an alternating stack of word-line-level electrically conductive layers and insulating layers; and source strips located on an opposite side of the source-select-level electrically conductive strips. Each of the source strips has an areal overlap with only a respective one of the source-select-level electrically conductive strips. Memory stack structures vertically extend through the alternating stack and a respective subset of the source-select-level electrically conductive strips. A logic die may be bonded to the memory die on an opposite side of the source strips. Each source strip is electrically connected to a respective group of memory stack structures laterally surrounded by a respective source-select-level electrically conductive strip.

公开(公告)号：US20240250023A1

公开(公告)日：2024-07-25

申请号：US18358702

申请日：2023-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ruogu Matthew ZHU ,  Koichi MATSUNO ,  Seyyed Ehsan Esfahani RASHIDI ,  Jixin YU ,  Johann ALSMEIER

IPC: H01L23/528 ,  G11C5/06 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C5/063 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L23/5226

Abstract: A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

公开(公告)号：US12046305B2

公开(公告)日：2024-07-23

申请号：US17665267

申请日：2022-02-04

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.

公开(公告)号：US12046289B2

公开(公告)日：2024-07-23

申请号：US17940498

申请日：2022-09-08

Applicant: SanDisk Technologies LLC

Inventor： Han-Ping Chen ,  Guirong Liang

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/3459

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.

公开(公告)号：US12046285B2

公开(公告)日：2024-07-23

申请号：US17351789

申请日：2021-06-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naoki Takeguchi ,  Masanori Tsutsumi ,  Seiji Shimabukuro ,  Tatsuya Hinoue

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

公开(公告)号：US12046267B2

公开(公告)日：2024-07-23

申请号：US17895803

申请日：2022-08-25

Applicant: SanDisk Technologies LLC

Inventor： Kazuki Yamauchi

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/10

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to program and verify the memory cells during a program operation. The memory cells associated with predetermined ones of the data states are not verified until the memory cells associated with specific prior ones of the data states finish programming to define verify windows ranging between each one of the specific prior ones of the data states and each one of the predetermined ones. The control means adjusts the verify windows in response to the memory cells associated with one of the specific prior ones of the data states not finishing programming before the one of the predetermined ones of the at least one of the verify windows is verified.