公开(公告)号：US07935738B2

公开(公告)日：2011-05-03

申请号：US12125328

申请日：2008-05-22

申请人： Chih-Kuang Chen ,  Shih-Ming Chen ,  Jia-Chi Huang ,  Young-Jen Lee ,  Li-Ching Wang

发明人： Chih-Kuang Chen ,  Shih-Ming Chen ,  Jia-Chi Huang ,  Young-Jen Lee ,  Li-Ching Wang

IPC分类号： C08F2/42 ,  C08F2/50 ,  C08K3/34 ,  C08K9/06 ,  C09K19/00

CPC分类号： C08K3/346 ,  C08J3/28 ,  C08J5/18 ,  Y10T428/10 ,  Y10T428/31504

摘要： A transparent flexible film is provided, formed by curing a composition, comprising: about 40-75 parts by weight of a clay; about 15-45 parts by weight of a water-soluble polymer; about 1-10 parts by weight of a mono-functional acrylic oligomer of formula (I), wherein n1 is an integer 2-25, R1 is C1-10 alkyl or H, and R2 is H or CH3; and about 10-45 parts by weight of a bi-functional acrylic oligomer of formula (II), wherein n2 is an integer 3-50, R3 and R4 are H or CH3.

摘要翻译： 提供通过固化组合物形成的透明柔性膜，其包含：约40-75重量份的粘土; 约15-45重量份的水溶性聚合物; 约1-10重量份式（I）的单官能丙烯酸低聚物，其中n1为2-25的整数，R1为C1-10烷基或H，R2为H或CH3; 和约10-45重量份的式（II）的双功能丙烯酸低聚物，其中n2是3-50的整数，R3和R4是H或CH3。

公开(公告)号：US20110062500A1

公开(公告)日：2011-03-17

申请号：US12953347

申请日：2010-11-23

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L29/80

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。

公开(公告)号：US07884471B2

公开(公告)日：2011-02-08

申请号：US11306015

申请日：2005-12-14

申请人： Yu-Ying Tsai ,  Shih-Ming Chen ,  Kuo-Wei Lin

发明人： Yu-Ying Tsai ,  Shih-Ming Chen ,  Kuo-Wei Lin

IPC分类号： H01L29/40

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

摘要： Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

摘要翻译： 本文公开了中间和焊料凸块结构。 在一个实施例中，结构包括主焊料柱，其包括主焊料材料并且被配置为电接触半导体衬底上的焊盘。 该结构还包括至少一个辅助焊料柱，其包括与主焊料柱电接触的次要焊料材料，所述至少一个第二柱具有小于主焊料柱的高度和体积的高度和体积。 在这种结构中，主焊料柱进一步构造成当中间结构经历回流工艺时，通过与至少一个次级焊料柱的内聚形成包括主焊料材料和至少一部分辅助焊料材料的主要焊料凸块 。

公开(公告)号：US07863742B2

公开(公告)日：2011-01-04

申请号：US11933572

申请日：2007-11-01

申请人： Hsiu-Mei Yu ,  Tjandra Winata Karta ,  Daniel Yang ,  Shih-Ming Chen ,  Chia-Jen Cheng

发明人： Hsiu-Mei Yu ,  Tjandra Winata Karta ,  Daniel Yang ,  Shih-Ming Chen ,  Chia-Jen Cheng

IPC分类号： H01L23/488

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552 ,  H01L2924/01004 ,  H01L2924/013 ,  H01L2924/01028 ,  H01L2924/0105

摘要： An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.

摘要翻译： 集成电路结构包括钝化层; 钝化层中的通孔; 通孔开口中的含铜通孔; 在所述钝化层上的聚合物层，其中所述聚合物层包括孔，并且其中所述含铜通孔通过所述孔露出; 在聚合物层上方的钝化后互连（PPI）线，其中PPI线延伸到孔中并物理接触铜通孔; 以及在PPI线上电连接的凸块下冶金（UBM）。

公开(公告)号：US20090236681A1

公开(公告)日：2009-09-24

申请号：US12177779

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US20080211997A1

公开(公告)日：2008-09-04

申请号：US12028029

申请日：2008-02-08

申请人： Shih-Ming Chen ,  Chyi-Ming Leu ,  Tzong-Ming Lee ,  Young-Jen Lee ,  Chia-Chi Huang ,  Chi-Fu Tseng

发明人： Shih-Ming Chen ,  Chyi-Ming Leu ,  Tzong-Ming Lee ,  Young-Jen Lee ,  Chia-Chi Huang ,  Chi-Fu Tseng

IPC分类号： G02F1/1335 ,  B32B27/28 ,  B32B5/16 ,  C09K19/02

CPC分类号： C08G73/10 ,  G02B5/305 ,  G02F1/133528 ,  G02F1/133634 ,  Y10T428/1041 ,  Y10T428/256 ,  Y10T428/258 ,  Y10T428/259 ,  Y10T428/266 ,  Y10T428/31721

摘要： A polarizing plate is provided. The polarizing plate includes a polarizing film, a first protective film and a second protective film respectively disposed on both sides of the polarizing film, and a polyimide optical compensation film having thickness direction retardation (Rth) or both, in-plane retardation (R0) and thickness direction retardation (Rth) disposed on the first protective film. The invention also provides a liquid crystal display including the polarizing plate.

摘要翻译： 提供了一种偏振片。 偏光板包括分别设置在偏振膜两侧的偏振膜，第一保护膜和第二保护膜，以及具有厚度方向延迟（Rth）或两者的面内延迟（R0）的聚酰亚胺光学补偿膜， 和厚度方向延迟（Rth）设置在第一保护膜上。 本发明还提供一种包括偏振片的液晶显示器。

公开(公告)号：US20080206456A1

公开(公告)日：2008-08-28

申请号：US12081468

申请日：2008-04-16

申请人： Anthony Shiaw-Tseh Chiang ,  Shih-Ming Chen ,  Young-Jen Lee

发明人： Anthony Shiaw-Tseh Chiang ,  Shih-Ming Chen ,  Young-Jen Lee

IPC分类号： B05D3/02 ,  B05D5/06

CPC分类号： G02B1/118 ,  C08J7/06 ,  G02B1/14 ,  Y10T428/249961 ,  Y10T428/249967 ,  Y10T428/249969 ,  Y10T428/24997 ,  Y10T428/249987

摘要： An antireflective transparent zeolite hardcoat and fabrication method thereof. The transparent zeolite hardcoat comprises a zeolite nanostructure made of zeolite nanocrystals vertically stacked into a porous structure on a substrate, wherein the porosity increases with structure height, thereby providing a smooth refractive index transition.

公开(公告)号：US20070267985A1

公开(公告)日：2007-11-22

申请号：US11747850

申请日：2007-05-11

申请人： Wen-Tsung Lin ,  Ching-Liang Lin ,  Shih-Ming Chen

发明人： Wen-Tsung Lin ,  Ching-Liang Lin ,  Shih-Ming Chen

IPC分类号： H05B39/00

CPC分类号： H05B41/2822 ,  H05B41/02

摘要： A display includes a backlight module having elongated lamps. At least a pair of the lamps has a first lamp and a second lamp that are electrically connected in series. The first lamp and the second lamp are spaced apart with at least a third lamp positioned between the first and second lamps.

摘要翻译： 显示器包括具有细长灯的背光模块。 至少一对灯具有串联地电连接的第一灯和第二灯。 第一灯和第二灯间隔开至少一个位于第一和第二灯之间的第三灯。

公开(公告)号：US20070188115A1

公开(公告)日：2007-08-16

申请号：US11656209

申请日：2007-01-22

申请人： Wen-Tsung Lin ,  Tz-Lung Su ,  Shih-Ming Chen

发明人： Wen-Tsung Lin ,  Tz-Lung Su ,  Shih-Ming Chen

IPC分类号： H05B39/00

CPC分类号： H05B41/2822 ,  H05B41/00

摘要： The backlight module includes a first lamp, a second lamp, a circuit board and a driving circuit board. The circuit board includes chambers to be connected to the first lamp and the second lamp, and capacitors to stabilize a voltage across two ends of each of the first lamp and the second lamp. The driving circuit board includes an inverter for driving the first lamp and the second lamp via the circuit board.

摘要翻译： 背光模块包括第一灯，第二灯，电路板和驱动电路板。 电路板包括要连接到第一灯和第二灯的室，以及用于稳定第一灯和第二灯中的每一个的两端的电压的电容器。 驱动电路板包括经由电路板驱动第一灯和第二灯的逆变器。

公开(公告)号：US20070020906A1

公开(公告)日：2007-01-25

申请号：US11185819

申请日：2005-07-21

申请人： Sung-Cheng Chiu ,  Hao-Yi Tsai ,  Hsiu-Mei Yu ,  Shih-Ming Chen ,  Shang-Yun Hou

发明人： Sung-Cheng Chiu ,  Hao-Yi Tsai ,  Hsiu-Mei Yu ,  Shih-Ming Chen ,  Shang-Yun Hou

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05017 ,  H01L2224/05027 ,  H01L2224/0554 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask. Thereafter, the electrically conductive material is reflowed to provide a bump on the semiconductor substrate.

摘要翻译： 提供了在半导体衬底上形成凸块的方法，其上具有接触垫的衬底。 在一个实施例中，该方法包括在衬底和接触垫上沉积钝化层。 对钝化层进行图案化和蚀刻以在钝化层中形成暴露接触焊盘部分的多个开口。 在蚀刻的钝化层上和其多个开口中沉积凸块下的冶金（UBM）层以接触接触焊盘。 在UBM层上形成光致抗蚀剂层，然后对其进行图案化和蚀刻以形成基本上覆盖接触焊盘的至少一个开口。 将导电材料沉积到形成在光致抗蚀剂层中的开口中，并覆盖UBM层并与接触垫对齐。 去除剩余光致抗蚀剂层的一部分。 使用导电材料作为掩模蚀刻UBM层。 此后，导电材料回流以在半导体衬底上提供凸块。