公开(公告)号：US20090283303A1

公开(公告)日：2009-11-19

申请号：US12266674

申请日：2008-11-07

Applicant: Chiang-Cheng Chang ,  Yen-Ping Wang ,  Don-Son Jiang ,  Jeng-Yuan Lai ,  Yu-Po Wang

Inventor： Chiang-Cheng Chang ,  Yen-Ping Wang ,  Don-Son Jiang ,  Jeng-Yuan Lai ,  Yu-Po Wang

IPC: H05K1/09

CPC classification number: H05K1/116 ,  H05K1/114 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.

Abstract translation: 提出了具有无地导电迹线的封装衬底，其包括形成在其中的多个电镀通孔的芯层和形成在芯层的至少表面上的多个导电迹线。 每个导电迹线具有连接端，接合焊盘端和连接连接端和接合焊盘端的基体，导电迹线通过连接端电连接到相应的一个电镀通孔，以及 连接端具有大于基体的宽度，但不大于电镀通孔的直径，从而增加导电迹线和电镀通孔之间的接触面积，并且防止导电迹线的接触表面与 电镀通孔破裂。

公开(公告)号：US07423340B2

公开(公告)日：2008-09-09

申请号：US11112107

申请日：2005-04-21

Applicant: Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L23/053 ,  H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L23/02

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US20080185726A1

公开(公告)日：2008-08-07

申请号：US12011906

申请日：2008-01-30

Applicant: Yu-Po Wang ,  Chien-Ping Huang ,  Wei-Chun Lin ,  Wen Cheng Lee

Inventor： Yu-Po Wang ,  Chien-Ping Huang ,  Wei-Chun Lin ,  Wen Cheng Lee

IPC: H01L23/49

CPC classification number: H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

Abstract translation: 本发明提出的半导体封装基板包括基体和设置在基体表面上的多个指垫，其中指垫以这样一种方式布置，使得两个相邻手指的中心的连接线之间形成一角度 垫和指垫的排列方向。 手指垫是具有弧端的水滴状指垫，并且角度端交替地设置在基板的表面上，交替地设置水滴形指状垫和弧形指状垫，或者以预定间隔交替布置的圆弧形指垫。 根据本发明，相邻指垫之间的距离减小，并且防止了接合线和相邻指垫之间的错误接触的结果导致的短路问题。

公开(公告)号：US20080108182A1

公开(公告)日：2008-05-08

申请号：US11928708

申请日：2007-10-30

Applicant: Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/68

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/58 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/007 ,  H05K3/3457 ,  H05K3/4682 ,  H05K2203/0152 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20080017983A1

公开(公告)日：2008-01-24

申请号：US11880467

申请日：2007-07-20

Applicant: Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract translation: 本发明公开了一种倒装芯片半导体封装及其芯片载体。 芯片载体包括围绕芯片安装区域形成的凹槽。 槽可以沿着芯片安装区域的周边或其拐角处形成。 凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

公开(公告)号：US20070273026A1

公开(公告)日：2007-11-29

申请号：US11701767

申请日：2007-02-02

Applicant: Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

Inventor： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

IPC: H01L23/488

CPC classification number: H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract translation: 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

公开(公告)号：US20060049516A1

公开(公告)日：2006-03-09

申请号：US11145318

申请日：2005-06-03

Applicant: Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

Inventor： Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

IPC: H01L23/48

CPC classification number: H05K3/243 ,  H01L21/563 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/064 ,  H05K3/3452 ,  H05K2201/09845 ,  H05K2203/0542 ,  Y02P70/611 ,  H01L2924/00

Abstract: A nickel/gold (Ni/Au) pad structure of a semiconductor package and a fabrication method thereof are provided. The fabrication method includes preparing a core layer; forming a conductive trace layer on the core layer; patterning the conductive trace layer to form at least one pad of the conductive trace layer; applying a conductive layer; forming a photoresist layer to define a predetermined plating region on the pad, wherein the predetermined plating region is smaller in area than the pad; forming a Ni/Au layer on the predetermined plating region; removing the photoresist layer and etching away the conductive layer; and applying a solder mask layer and forming at least one opening in the solder mask layer to expose the pad, wherein the opening is larger in area than the Ni/Au layer. The Ni/Au pad structure fabricated by the above method can prevent a solder extrusion effect incurred in the conventional technology.

Abstract translation: 提供半导体封装的镍/金（Ni / Au）焊盘结构及其制造方法。 制造方法包括制备芯层; 在芯层上形成导电迹线层; 图案化导电迹线层以形成至少一个导电迹线层的焊盘; 施加导电层; 形成光致抗蚀剂层以在所述焊盘上限定预定的镀覆区域，其中所述预定电镀区域的面积小于所述焊盘; 在预定的电镀区上形成Ni / Au层; 去除光致抗蚀剂层并蚀刻掉导电层; 以及施加焊接掩模层并在所述焊料掩模层中形成至少一个开口以露出所述焊盘，其中所述开口面积大于所述Ni / Au层。 通过上述方法制造的Ni / Au焊盘结构可以防止传统技术中引起的焊料挤出效应。

公开(公告)号：US20050253284A1

公开(公告)日：2005-11-17

申请号：US10972200

申请日：2004-10-22

Applicant: Yu-Po Wang ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

Inventor： Yu-Po Wang ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/13 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.

Abstract translation: 提出了一种半导体封装及其制造方法。 提供了具有形成在第一和第二电路层之间的第一电路层，第二电路层和芯层的衬底。 在第二电路层上形成至少一个第二开口。 在对应于第二开口的第一电路层上形成至少一个第一开口。 在芯层中形成与第一电路层上的接合指状对应的多个指孔。 在芯层中形成通孔，并与第一和第二开口连通。 至少一个芯片安装在第一电路层上并且覆盖第一开口，其有源表面暴露于第一开口。 形成密封剂以填充第一和第二开口和通孔并封装芯片。

公开(公告)号：US20050194667A1

公开(公告)日：2005-09-08

申请号：US11112108

申请日：2005-04-21

Applicant: Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US20050194665A1

公开(公告)日：2005-09-08

申请号：US11112106

申请日：2005-04-21

Applicant: Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。