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    Semiconductor memory device performing auto refresh in the self refresh mode
    31.
    发明授权
    Semiconductor memory device performing auto refresh in the self refresh mode 有权
    在自刷新模式下执行自动刷新的半导体存储器件

    公开(公告)号：US07164615B2

    公开(公告)日：2007-01-16

    申请号：US11169241

    申请日：2005-06-27

    Applicant: Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

    Inventor： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

    Abstract: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

    Abstract translation: 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。

    High burst rate write data paths for integrated circuit memory devices and methods of operating same
    32.
    发明授权
    High burst rate write data paths for integrated circuit memory devices and methods of operating same 有权
    用于集成电路存储器件的高突发速率写入数据路径及其操作方法

    公开(公告)号：US07054202B2

    公开(公告)日：2006-05-30

    申请号：US10792425

    申请日：2004-03-03

    Applicant: Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

    Inventor： Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

    IPC: G11C16/04

    CPC classification number: G11C7/1078 ,  G11C7/1027 ,  G11C2207/107

    Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

    Abstract translation: 集成电路存储器件包括被配置为并行地写入N个数据位的存储器单元阵列和被配置为从外部端子串行地接收2N个数据位的写入数据路径。 写数据路径包括2N个写入数据缓冲器，其被配置为存储2N个数据位，2N个开关和N个数据线，其被配置为将2N个开关中的至少N个连接到存储单元阵列以在其中写入N个数据位 平行。 可以提供减少数量的本地数据线和/或全局数据线。

    Bit line sensing control circuit for a semiconductor memory device and layout of the same
    33.
    发明授权
    Bit line sensing control circuit for a semiconductor memory device and layout of the same 有权
    用于半导体存储器件的位线检测控制电路及其布局

    公开(公告)号：US06473325B2

    公开(公告)日：2002-10-29

    申请号：US09882209

    申请日：2001-06-15

    Applicant: Yun-Sang Lee ,  Sang-Suk Kang ,  Jae-Hoon Joo ,  Jong-Eon Lee

    Inventor： Yun-Sang Lee ,  Sang-Suk Kang ,  Jae-Hoon Joo ,  Jong-Eon Lee

    IPC: G11C506

    CPC classification number: G11C7/065 ,  G11C11/4074 ,  G11C11/4091

    Abstract: A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and is connected to an active area surrounded by the power gate through the power contact.

    Abstract translation: 半导体存储器件的位线检测控制电路的布局包括沿第一方向延伸的两个位线对。 电源触点设置在两个位线对之间。 电源端口设置在电源触点周围。 多个感测晶体管分别具有多个感测晶体管栅极。 多个感测晶体管栅极布置在功率门周围。 一对控制线触点在两个位线对之外的相邻位置处沿第二方向布置。 控制线在第二方向上延伸并且通过一对控制线触点连接到电源门。 电力线在与控制线相邻的第二方向上延伸，并且通过电力接触连接到被电力门围绕的有效区域。

    Integrated circuit memory devices including rows of pads extending parallel to the short sides of the integrated circuit
    34.
    发明授权
    Integrated circuit memory devices including rows of pads extending parallel to the short sides of the integrated circuit 有权
    集成电路存储器件，包括平行于集成电路的短边延伸的衬垫行

    公开(公告)号：US6069812A

    公开(公告)日：2000-05-30

    申请号：US136831

    申请日：1998-08-20

    Applicant: Yun-sang Lee ,  Jun-young Jeon

    Inventor： Yun-sang Lee ,  Jun-young Jeon

    IPC: G11C11/401 ,  G11C5/02 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: G11C5/025

    Abstract: Integrated circuit memory devices include a rectangular integrated circuit memory device substrate that includes a pair of short sides, a pair of long sides and a pair of opposing faces. The substrate also includes an array of memory cells and peripheral circuits therein. A plurality of spaced apart rows of input/output pads on one of the faces extend parallel to the short sides. The face is free of (i.e. does not include) a row of input/output pads that extends parallel to the long sides. The input/output pads are preferably arranged on the integrated circuit memory device substrate, relative to the circuits in the integrated circuit memory device substrate. More specifically, the integrated circuit memory device includes a plurality of memory cell array blocks, first decoder blocks and second decoder blocks in the substrate. A respective first decoder block extends parallel to the short sides adjacent a respective memory cell array block and opposite a short side. A respective second decoder block extends parallel to the long sides, between adjacent memory cell array blocks. The plurality of input/output pads are included between the short sides and the memory cell array blocks adjacent thereto and between the first decoder blocks.

    Abstract translation: 集成电路存储器件包括矩形集成电路存储器件衬底，其包括一对短边，一对长边和一对相对面。 衬底还包括其中的存储器单元阵列和外围电路。 在其中一个面上的多个间隔开的输入/输出焊盘行平行于短边延伸。 脸部没有（即不包括）一排平行于长边延伸的输入/输出垫片。 相对于集成电路存储器件衬底中的电路，输入/输出焊盘优选地布置在集成电路存储器件衬底上。 更具体地，集成电路存储器件包括衬底中的多个存储单元阵列块，第一解码器块和第二解码器块。 相应的第一解码器块平行于相邻的存储单元阵列块的短边延伸并且与短边相对。 相应的第二解码器块在相邻的存储单元阵列块之间平行于长边延伸。 多个输入/输出焊盘包括在短边和与其相邻的存储单元阵列块之间和第一解码器块之间。

    Data output circuit of a semiconductor memory device
    35.
    发明授权
    Data output circuit of a semiconductor memory device 失效
    半导体存储器件的数据输出电路

    公开(公告)号：US5396463A

    公开(公告)日：1995-03-07

    申请号：US973690

    申请日：1992-11-09

    Applicant: Young-Rae Kim ,  Yun-Sang Lee

    Inventor： Young-Rae Kim ,  Yun-Sang Lee

    IPC: G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  H03K17/687 ,  H03K19/0175 ,  G11C7/00

    CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106

    Abstract: A data output circuit of a semiconductor memory circuit with pull-up and pull-down transistors for outputting data through complementary switching operation, comprising a pre-charge means for pre-charging a pair of data signals read from a memory cell having a given voltage level in a first operational mode, a switching means for connecting the output signal of the pre-charge means amplified to the gates of the pull-up and pull-down transistors, and an enable circuit for connecting the output signal of the switching means to the gates of the pull-up and pull-down transistors in a second operational mode. The switching means is a level change circuit to control the pull-up and pull-down transistors, which are data output drivers, by employing a constant voltage source to provide a voltage rise Vpp increased over the source voltage level Vcc of an integrated circuit before enabling the integrated circuit. The first and second operational mode respectively represent the disabling and enabling of the data output circuit to output the data.

    Abstract translation: 具有用于通过互补开关操作输出数据的上拉和下拉晶体管的半导体存储器电路的数据输出电路，包括用于对从具有给定电压的存储器单元读取的一对数据信号进行预充电的预充电装置 电平处于第一操作模式，用于连接放大到上拉和下拉晶体管的栅极的预充电装置的输出信号的开关装置和用于将开关装置的输出信号连接到 上拉和下拉晶体管的栅极处于第二操作模式。 开关装置是一个电平变化电路，用于通过采用恒压源来提供上升和下拉晶体管，作为数据输出驱动器，以提供在集成电路的源极电压电平Vcc之前增加的电压上升Vpp 启用集成电路。 第一和第二操作模式分别表示数据输出电路的禁用和使能以输出数据。

    SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME
    39.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME 有权
    具有电阻记忆体的半导体存储器件及其测试方法

    公开(公告)号：US20140022836A1

    公开(公告)日：2014-01-23

    申请号：US13945007

    申请日：2013-07-18

    Applicant: Hye-Jin KIM ,  Hyung-Rok OH ,  Dong-Seok KANG ,  Dong-Hyun SOHN ,  Sang-Beom KANG ,  Chul-Woo PARK ,  Yun-Sang LEE

    Inventor： Hye-Jin KIM ,  Hyung-Rok OH ,  Dong-Seok KANG ,  Dong-Hyun SOHN ,  Sang-Beom KANG ,  Chul-Woo PARK ,  Yun-Sang LEE

    IPC: G11C29/10 ,  G11C11/16

    CPC classification number: G11C29/10 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/32 ,  G11C29/34 ,  G11C2029/2602

    Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

    Abstract translation: 半导体存储器件包括存储单元阵列，模式寄存器组和测试电路。 存储单元阵列包括多个字线，多个位线和多个自旋转移转矩磁阻随机存取存储器（STT-MRAM）单元，每个STT-MRAM单元设置在每个字线的交叉区域 和位线，并且STT-MRAM单元包括磁隧道结（MTJ）元件和单元晶体管。 MTJ元件包括自由层，阻挡层和钉扎层。 单元晶体管的栅极耦合到字线，单元晶体管的第一电极通过MTJ元件耦合到位线，并且单元晶体管的第二电极耦合到源极线。 模式寄存器组被配置为设置测试模式，并且测试电路被配置为通过使用模式寄存器集执行测试操作。

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