公开(公告)号：US20120159128A1

公开(公告)日：2012-06-21

申请号：US12969812

申请日：2010-12-16

申请人： Raul Gutierrez ,  Suryaprasad Kareenahalli ,  Daniel Nemiroff ,  Balaji Vembu

发明人： Raul Gutierrez ,  Suryaprasad Kareenahalli ,  Daniel Nemiroff ,  Balaji Vembu

IPC分类号： G06F9/30

CPC分类号： G06F9/345 ,  G06F9/30018 ,  G06F9/3009 ,  G06F9/3851 ,  H04L49/90

摘要： In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明涉及一种位处理器，其包括执行单元，响应于访问第一位宽度的数据的指令，第二位宽度的访问数据，具有不同数量的第二位宽度 当某些访问的数据包括非流数据时，比第一位宽的位数。 描述和要求保护其他实施例。

公开(公告)号：US20110299680A1

公开(公告)日：2011-12-08

申请号：US12796502

申请日：2010-06-08

申请人： Balaji Vembu ,  Suryaprasad Kareenahalli ,  Daniel Nemiroff ,  Zohar Bogin ,  Raul Gutierrez

发明人： Balaji Vembu ,  Suryaprasad Kareenahalli ,  Daniel Nemiroff ,  Zohar Bogin ,  Raul Gutierrez

IPC分类号： H04L9/00

CPC分类号： H04N21/4405 ,  G06F21/10 ,  H04N21/4181 ,  H04N21/42623 ,  H04N21/4408

摘要： An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.

摘要翻译： 提出了一种用于安全播放的设备。 在一个实施例中，该装置包括控制器，该控制器包括用于管理认证和密钥推导的密钥导出模块。 在一个实施例中，如果可以检索数据流中的视频数据部分而不必对数据流进行解密，则该装置向图形引擎提供视频解密密钥。 在一个实施例中，该装置还包括解密模块，用于结合加密密钥对一部分数据进行解密以产生视频信息和视频数据。 然后，控制器将视频数据的加密版本写入图形引擎的视频缓冲器。

公开(公告)号：US20110037770A1

公开(公告)日：2011-02-17

申请号：US12912630

申请日：2010-10-26

申请人： Balaji Vembu ,  Aditya Navale ,  Wishwesh A. Gandhi

发明人： Balaji Vembu ,  Aditya Navale ,  Wishwesh A. Gandhi

IPC分类号： G09G5/39

CPC分类号： G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

摘要： A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

摘要翻译： 一种用于创建，更新和使用访客物理地址（GPA）以主机物理地址（HPA）影子转换表的方法和装置，用于将实现虚拟机监视器的计算环境的图形数据直接存储器访问（DMA）请求的GPA转换为 支持虚拟机。 可以通过虚拟机监视器透明地从一个或多个虚拟机通过计算环境的呈现或显示路径发送请求。 创建，更新和使用可以由存储器控制器执行，该存储器控制器检测发送到现有全局和页目录表的条目，从检测到的条目中分离影子表条目，以及将影子表条目的GPA转换为HPA。

公开(公告)号：US11768781B2

公开(公告)日：2023-09-26

申请号：US17827556

申请日：2022-05-27

申请人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

发明人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC分类号： G06F9/455 ,  G06F9/50 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

CPC分类号： G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10424043B1

公开(公告)日：2019-09-24

申请号：US16025718

申请日：2018-07-02

申请人： Joseph Koston ,  Ankur Shah ,  Murali Ramadoss ,  Jeffery Boles ,  Balaji Vembu

发明人： Joseph Koston ,  Ankur Shah ,  Murali Ramadoss ,  Jeffery Boles ,  Balaji Vembu

IPC分类号： G06T1/20 ,  G06F21/74 ,  G06T15/00 ,  G06F9/50 ,  G06T1/60 ,  G09G5/36

摘要： Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing cores, a shared buffer accessible to a user mode driver (UMD) associated with an application in an unprivileged domain, the UMD to write one or more commands to the shared buffer, and a controller parse a workload in the shared buffer to identify one or more commands in the workload, the workload added by the application executing in the unprivileged domain, associate a trigger with a command in the workload, transfer the workload to one or more components of the graphics processing apparatus for execution, and upon execution of the command associated with the trigger, sample the shared buffer to identify a new workload added to the shared buffer. The one or more components of the graphics processing apparatus automatically execute the new workload added to the shared buffer.

公开(公告)号：US20180308200A1

公开(公告)日：2018-10-25

申请号：US15494886

申请日：2017-04-24

申请人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06F17/16 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F2009/45583 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type

公开(公告)号：US20180095785A1

公开(公告)日：2018-04-05

申请号：US15281260

申请日：2016-09-30

申请人： Altug Koker ,  Prassonkumar Surti ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Balaji Vembu

发明人： Altug Koker ,  Prassonkumar Surti ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Balaji Vembu

IPC分类号： G06F9/48

CPC分类号： G06F9/4831 ,  G06F9/4881

摘要： A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a thread dispatcher to assign a priority class to each of a plurality of processing threads prior to dispatching the one or more processing threads, a plurality of execution units to process the threads, a shared resource coupled to each of the plurality of execution units and an arbitration unit to grant access to the shared resource to a first of the plurality of execution units based on the priority class of a thread being executed at the first execution unit.

公开(公告)号：US09501668B2

公开(公告)日：2016-11-22

申请号：US14036263

申请日：2013-09-25

申请人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

发明人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

IPC分类号： H04N7/167 ,  G06F21/82 ,  G06F21/84 ,  G06F21/85 ,  H04N21/41 ,  H04N21/4143 ,  H04N21/4367

CPC分类号： G06F21/82 ,  G06F21/84 ,  G06F21/85 ,  H04N21/4122 ,  H04N21/4143 ,  H04N21/4367

摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.

摘要翻译： 用于将输出表面位图安全传递到显示引擎的系统和方法。 一个示例处理系统包括：架构受保护的存储器; 以及处理核心，其通信地耦合到所述体系结构保护的存储器，所述处理核心包括处理逻辑，所述处理逻辑被配置为通过执行以下中的至少一个来实现架构保护的执行环境：执行驻留在所述体系结构保护的存储器中的指令， 建筑保护记忆; 其中所述处理逻辑还被配置为通过生成用第一加密密钥加密并将加密的第一加密密钥存储在外部存储器中的输出表面位图来提供安全视频输出路径，其中所述加密的第一加密密钥是通过加密所述第一加密密钥 具有第二加密密钥的加密密钥。

公开(公告)号：US20140208047A1

公开(公告)日：2014-07-24

申请号：US13977295

申请日：2011-12-28

申请人： Balaji Vembu ,  Murali Ramadoss

发明人： Balaji Vembu ,  Murali Ramadoss

IPC分类号： G06F3/06

CPC分类号： G06F3/0638 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0292 ,  G06F2212/205 ,  G06T1/60 ,  G11C14/0045 ,  Y02D10/13

摘要： A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device, storing one or more static data segments of the software application in the PCMS device, and storing one or more volatile data segments of the software application in a volatile memory device. The method then allocates an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

摘要翻译： 描述了在易失性和非易失性存储器之间分发代码和数据存储的方法，设备和系统。 在一个实施例中，该方法包括将具有交换机（PCMS）设备的软件应用的一个或多个静态代码段存储在相变存储器中，将该软件应用的一个或多个静态数据段存储在PCMS设备中，并存储一个或多个 在易失性存储器件中软件应用的更易变的数据段。 该方法然后将至少一个第一地址指针的地址映射表分配给一个或多个静态代码段中的每一个，至少第二地址指针指向一个或多个静态数据段中的每一个，并且至少 指向一个或多个易失性数据段中的每一个的第三地址指针。

公开(公告)号：US20140176572A1

公开(公告)日：2014-06-26

申请号：US13724291

申请日：2012-12-21

申请人： Balaji Vembu ,  David I. Poisner ,  Arvind Kumar ,  Chaitanya R. Gandra

发明人： Balaji Vembu ,  David I. Poisner ,  Arvind Kumar ,  Chaitanya R. Gandra

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： In an embodiment, a processor includes a graphics domain including a graphics engines each having at least one execution unit. The graphics domain is to schedule a touch application offloaded from a core domain to at least one of the plurality of graphics engines. The touch application is to execute responsive to an update to a doorbell location in a system memory coupled to the processor, where the doorbell location is written responsive to a user input to the touch input device. Other embodiments are described and claimed.