公开(公告)号：US06610560B2

公开(公告)日：2003-08-26

申请号：US09854303

申请日：2001-05-11

Applicant: Han-Ping Pu ,  Yu-Po Wang ,  Caesar Lin

Inventor： Han-Ping Pu ,  Yu-Po Wang ,  Caesar Lin

IPC: H01L2144

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L21/565 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A semiconductor packaging technology is proposed for the fabrication of a chip-on-chip (COC) based multi-chip module (MCM) with molded underfill. The proposed semiconductor packaging technology is characterized by the provision of a side gap of an empirically-predetermined width between the overlying chips mounted through COC technology over an underlying chip to serve as an air vent during molding process. This allows the injected molding material to flow freely into the flip-chip undergaps during molding process. In actual application, the exact width of the side gap is empirically predetermined through molded-underfill simulation experiments to find the optimal value. Based on experimental data, it is found that this side gap width should be equal to or less than 0.3 mm to allow optimal underfill effect. The optimal value for this side gap width may be varied for different package specifications.

公开(公告)号：US20080164604A1

公开(公告)日：2008-07-10

申请号：US12008202

申请日：2008-01-08

Applicant: Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Liang-Yi Hung ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/34

CPC classification number: H01L23/3675 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2224/0401

Abstract: A heat dissipating semiconductor package is disclosed, including a chip carrier; at least a semiconductor chip mounted and electrically connected to the chip carrier; and a heat dissipating member mounted on the semiconductor chip with a thermal interface material (TIM) interposed therebetween, wherein the TIM is provided with a plurality of fillers for supporting the TIM at an appropriate height, thereby preventing the TIM from being wetted so as to avoid collapsing and overflow of the TIM as a result of wetting problem.

Abstract translation: 公开了一种散热半导体封装，包括芯片载体; 至少安装并电连接到所述芯片载体的半导体芯片; 以及安装在半导体芯片上的散热构件，其间插入有热界面材料（TIM），其中所述TIM具有多个用于将TIM支撑在适当高度的填充物，从而防止TIM被润湿，从而 避免由于润湿问题导致TIM的崩溃和溢出。

公开(公告)号：US20070249101A1

公开(公告)日：2007-10-25

申请号：US11821269

申请日：2007-06-22

Applicant: Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/60

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20050194666A1

公开(公告)日：2005-09-08

申请号：US11112107

申请日：2005-04-21

Applicant: Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US08901729B2

公开(公告)日：2014-12-02

申请号：US13490810

申请日：2012-06-07

Applicant: Chia-Yin Chen ,  Yu-Ching Liu ,  Yueh-Chiung Chang ,  Yu-Po Wang

Inventor： Chia-Yin Chen ,  Yu-Ching Liu ,  Yueh-Chiung Chang ,  Yu-Po Wang

IPC: H01L23/48

CPC classification number: H01L24/03 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/03462 ,  H01L2224/03552 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/27013 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Abstract translation: 提供了使用封装基板的封装基板和半导体封装。 封装基板包括：具有管芯附着区域的基板主体，形成在管芯附着区域周围的电路层，并且具有多个导线，每个导线具有引线焊盘，以及形成在引线接合焊盘上的表面处理层。 其中，仅有一个导电迹线连接到电镀线，以便防止由于现有技术中的电镀线太多导致的导电迹线之间的串扰。

公开(公告)号：US08207620B2

公开(公告)日：2012-06-26

申请号：US11880467

申请日：2007-07-20

Applicant: Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Yuan-Lin Tzeng ,  Nai-Hao Kao ,  Jeng-Yuan Lai ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/29

CPC classification number: H01L21/563 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract translation: 本发明公开了一种倒装芯片半导体封装及其芯片载体。 芯片载体包括围绕芯片安装区域形成的凹槽。 槽可以沿着芯片安装区域的周边或其拐角处形成。 凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

公开(公告)号：US07732913B2

公开(公告)日：2010-06-08

申请号：US11701767

申请日：2007-02-02

Applicant: Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

Inventor： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

IPC: H01L23/04

CPC classification number: H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract translation: 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

公开(公告)号：US07564140B2

公开(公告)日：2009-07-21

申请号：US11411740

申请日：2006-04-25

Applicant: Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

Abstract translation: 提供半导体封装及其基板结构。 施加在基板结构上的焊接掩模层形成有对应于基板结构的芯片安装区域的角部的向外延伸的开口。 当倒装芯片半导体芯片安装在芯片安装区域并执行底部填充工艺时，底部填充材料可以填充倒装芯片半导体芯片和基板结构之间的间隙，并且有效地填充焊料的向外延伸的开口 掩模层对应于芯片安装区域的角部，以便为倒装芯片半导体芯片的拐角提供足够的保护，并防止在随后的热循环期间倒装芯片半导体芯片的拐角处的分层。

公开(公告)号：US07361846B2

公开(公告)日：2008-04-22

申请号：US10974376

申请日：2004-10-26

Applicant: Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

Inventor： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

IPC: H05K1/16

CPC classification number: H01L23/49838 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

Abstract translation: 提出了一种高性能半导体封装。 提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。 芯片附接到载体的第一表面。 多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。 多个导电区域设置在载体的第二表面上并电连接到通孔。 多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。 多个接合线将芯片电连接到手指。 用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。

公开(公告)号：US20070096336A1

公开(公告)日：2007-05-03

申请号：US11411740

申请日：2006-04-25

Applicant: Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Wen-Hao Lee ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

Abstract translation: 提供半导体封装及其基板结构。 施加在基板结构上的焊接掩模层形成有对应于基板结构的芯片安装区域的角部的向外延伸的开口。 当倒装芯片半导体芯片安装在芯片安装区域并执行底部填充工艺时，底部填充材料可以填充倒装芯片半导体芯片和基板结构之间的间隙，并且有效地填充焊料的向外延伸的开口 掩模层对应于芯片安装区域的角部，以便为倒装芯片半导体芯片的拐角提供足够的保护，并防止在随后的热循环期间倒装芯片半导体芯片的拐角处的分层。