ON-SIGNAL QUADRATURE MODULATOR CALIBRATION
    31.
    发明申请
    ON-SIGNAL QUADRATURE MODULATOR CALIBRATION 有权
    信号量程调制器校准

    公开(公告)号:US20050075815A1

    公开(公告)日:2005-04-07

    申请号:US10666410

    申请日:2003-09-19

    CPC classification number: H04L27/364 H03C3/406 H03D3/008 H03D3/009 H04B17/14

    Abstract: An on-signal calibration system I and Q signals of a transmitter to remove distortions in the RF output signal. The transmitter generates I and Q values and converts, modulates and combines the I and Q values into the RF output signal for transmission. The calibration system includes a detector, a sampler, a selector, an imbalance estimator, and an IQ corrector. The detector senses the RF output signal and provides a detection signal indicative thereof. The sampler samples the detection signal and provides digital samples. The selector selects from among the digital samples that correspond to predetermined ranges of the I and Q values, or otherwise predetermined selection boxes at predetermined phases. The imbalance estimator determines at least one imbalance estimate based on selected digital samples. The IQ corrector corrects the I and Q values using at least one imbalance estimate.

    Abstract translation: 发射机的信号校准系统I和Q信号,以消除RF输出信号中的失真。 发射机产生I和Q值,并将I和Q值转换,调制和组合成RF输出信号进行传输。 校准系统包括检测器,采样器,选择器,不平衡估计器和IQ校正器。 检测器感测RF输出信号并提供指示其的检测信号。 采样器对检测信号进行采样,并提供数字采样。 选择器从数字样本中选择对应于I和Q值的预定范围,或者在预定阶段选择预定的选择框。 不平衡估计器基于所选择的数字样本确定至少一个不平衡估计。 IQ校正器使用至少一个不平衡估计来校正I和Q值。

    Optical Modulators With Controllable Chirp
    34.
    发明申请
    Optical Modulators With Controllable Chirp 有权
    具有可控啁啾的光学调制器

    公开(公告)号:US20110222813A1

    公开(公告)日:2011-09-15

    申请号:US13032899

    申请日:2011-02-23

    Abstract: A semiconductor-based optical modulator is presented that includes a separate phase control section to adjust the amount of chirp present in the modulated output signal. At least one section is added to the modulator configuration and driven to create a pure “phase” signal that will is added to the output signal and modify the eiφ term inherent in the modulation function. The phase modulation control section may be located within the modulator itself (with one segment on each arm, driven by the same input signal), or may be disposed “outside” of the modulator on either the input waveguiding section or the output waveguiding section. The phase control section may be formed to comprise multiple segments (of different lengths), with the overall phase added to the propagating signal controlled by selecting the different segments to be energized to impart a phase delay to a signal propagating through the energized section(s).

    Abstract translation: 提出了一种基于半导体的光调制器,其包括单独的相位控制部分,用于调节调制输出信号中存在的线性调频音量。 至少一个部分被添加到调制器配置并被驱动以产生将被添加到输出信号并且修改ei&phgr的纯“相”信号。 术语固有的调制功能。 相位调制控制部分可以位于调制器本身内(每个臂上的一个段由相同的输入信号驱动),或者可以设置在输入波导部分或输出波导部分上的调制器的“外部”。 相位控制部分可以形成为包括多个段(不同长度),其中通过选择不同的被激励的段来控制传播信号的总相位,以向通过通电部分传播的信号施加相位延迟 )。

    Silicon-Based Schottky Barrier Detector With Improved Responsivity
    35.
    发明申请
    Silicon-Based Schottky Barrier Detector With Improved Responsivity 有权
    具有改善响应性的硅基肖特基势垒检测器

    公开(公告)号:US20110221019A1

    公开(公告)日:2011-09-15

    申请号:US13038470

    申请日:2011-03-02

    CPC classification number: H01L31/101 H01L31/1085

    Abstract: A planar, waveguide-based silicon Schottky barrier photodetector includes a third terminal in the form of a field plate to improve the responsivity of the detector. Preferably, a silicide used for the detection region is formed during a processing step where other silicide contact regions are being formed. The field plate is preferably formed as part of the first or second layer of CMOS metallization and is controlled by an applied voltage to modify the electric field in the vicinity of the detector's silicide layer. By modifying the electric field, the responsivity of the device is “tuned” so as to adjust the momentum of “hot” carriers (electrons or holes, depending on the conductivity of the silicon) with respect to the Schottky barrier of the device. The applied potential functions to align with the direction of momentum of the “hot” carriers in the preferred direction “normal” to the silicon-silicide interface, allowing for an increased number to move over the Schottky barrier and add to the generated photocurrent.

    Abstract translation: 平面的基于波导的硅肖特基势垒光电检测器包括场板形式的第三端子,以提高检测器的响应度。 优选地,在其中形成其它硅化物接触区域的处理步骤期间形成用于检测区域的硅化物。 场板优选地形成为第一或第二CMOS金属化层的一部分,并且通过施加的电压来控制,以修改检测器硅化物层附近的电场。 通过修改电场,器件的响应度被“调谐”,以相对于器件的肖特基势垒调节“热”载流子(电子或空穴,取决于硅的导电性)的动量。 所施加的电位功能与“硅”载体的优势方向“正常”硅硅化物界面的动量方向相一致,允许增加的数量移动到肖特基势垒上并增加产生的光电流。

    SOI-based tunable laser
    37.
    发明授权
    SOI-based tunable laser 有权
    基于SOI的可调谐激光器

    公开(公告)号:US07701985B2

    公开(公告)日:2010-04-20

    申请号:US12291246

    申请日:2008-11-06

    Abstract: A silicon-on-insulator (SOI)-based tunable laser is formed to include the gain medium (such as a semiconductor optical amplifier) disposed within a cavity formed within the SOI substrate. A tunable wavelength reflecting element and associated phase matching element are formed on the surface of the SOI structure, with optical waveguides formed in the surface SOI layer providing the communication between these components. The tunable wavelength element is controlled to adjust the optical wavelength. Separate discrete lensing elements may be disposed in the cavity with the gain medium, providing efficient coupling of the optical signal into the SOI waveguides. Alternatively, the gain medium itself may be formed to include spot converting tapers on its endfaces, the tapers used to provide mode matching into the associated optical waveguides.

    Abstract translation: 形成绝缘体上硅(SOI)的可调谐激光器以包括设置在形成于SOI衬底内的空腔内的增益介质(例如半导体光放大器)。 在SOI结构的表面上形成可调波长反射元件和相关的相位匹配元件,其中形成在表面SOI层中的光波导提供这些部件之间的连通。 可调波长元件被控制以调节光学波长。 单独的离散透镜元件可以用增益介质设置在空腔中,从而提供光信号到SOI波导的有效耦合。 或者,增益介质本身可以被形成为包括其端面上的点变换锥度,用于向相关联的光波导提供模式匹配的锥度。

    Coupling between free space and optical waveguide using etched coupling surfaces
    38.
    发明申请
    Coupling between free space and optical waveguide using etched coupling surfaces 有权
    使用蚀刻的耦合表面在自由空间和光波导之间耦合

    公开(公告)号:US20090162013A1

    公开(公告)日:2009-06-25

    申请号:US12316540

    申请日:2008-12-11

    CPC classification number: G02B6/32 G02B6/305 G02B6/327

    Abstract: A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.

    Abstract translation: 使用基于等离子体的蚀刻工艺来将支撑光波导的光学基板的端面特别地成形为轮廓刻面,这将提高波导与自由空间光信号之间的耦合效率。 使用标准光刻技术对光学端面小平面进行图案化和刻蚀的能力允许形成任何所需的刻面几何形状,并跨越制造的整组组件在晶片的表面上复制。 可以使用适当限定的光刻掩模将透镜蚀刻到端面中,相对于光波导的参数和传播的自由空间信号选择透镜的焦点。 或者,可以沿着端面形成成角度的小面,其角度足以将反射/散射信号重新引导远离光轴。

    SOI structure including nanotaper with improved alignment capabilities to external light guide
    39.
    发明申请
    SOI structure including nanotaper with improved alignment capabilities to external light guide 审中-公开
    SOI结构包括具有改进的对外部光导对准能力的纳米锥

    公开(公告)号:US20090065682A1

    公开(公告)日:2009-03-12

    申请号:US12228619

    申请日:2008-08-13

    Applicant: Mark Webster

    Inventor: Mark Webster

    CPC classification number: G02B6/1228 G02B6/136

    Abstract: An arrangement for providing alignment between an optical nanotaper coupler and a free space optical signal includes the formation of a “ridge” structure around the location of the nanotaper coupler to reduce stray light-related errors in the alignment process. The ridge is preferably formed by etching vertical sidewalls through the inter-level dielectric (ILD) and buried oxide (BOX) layers of the SOI structure. When an optical source (such as an illuminated fiber, laser, etc.) is scanned across this etched arrangement, the signal received by an associated photodetector registers an increase at the boundary between the etched region and the vertical sidewall of the ridge, thus defining the bounds within which the nanotaper coupler is located. Since the dimensions of the ridge are known and controlled by the etching process, the location of the nanotaper coupler tip along the endface of the ridge can be determined from this scan.

    Abstract translation: 用于在光学纳米锥耦合器和自由空间光信号之间提供对准的装置包括在纳米锥耦合器的位置周围形成“脊”结构,以减少对准过程中的杂散光相关误差。 优选地,通过蚀刻通过SOI结构的层间电介质(ILD)和掩埋氧化物(BOX)层的垂直侧壁来形成脊。 当光源(如照明光纤,激光等)在该蚀刻装置上扫描时,由相关联的光电探测器接收的信号记录在蚀刻区域和脊的垂直侧壁之间的边界处的增加,从而限定 纳米锥耦合器所在的界限。 由于脊的尺寸是已知的并且通过蚀刻处理来控制,所以可以从该扫描确定纳米锥联接器尖端沿着脊的端面的位置。

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