公开(公告)号：US20080087992A1

公开(公告)日：2008-04-17

申请号：US11906136

申请日：2007-09-28

申请人： Lei Shi ,  Ming Sun ,  Kai Liu

发明人： Lei Shi ,  Ming Sun ,  Kai Liu

IPC分类号： H01L23/495

CPC分类号： H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

摘要翻译： 公开了半导体封装。 封装包括具有漏极，源极和栅极引线的引线框架以及耦合到引线框架的半导体管芯，该半导体管芯具有多个金属化源极触点。 桥接源极板互连具有桥接部分，设置在桥接部分的任一侧上的谷部分，设置在谷部分和桥接部分两侧的平面部分以及从平面部分之一悬挂的连接部分， 将源极引线与多个金属化源触点连接的源极板互连。 桥面部分设置在平坦部分的平面上方的平面中，而平面部分设置在桥接部分的平面和谷部的平面之间的平面中。

公开(公告)号：US20060145319A1

公开(公告)日：2006-07-06

申请号：US11027081

申请日：2004-12-31

申请人： Ming Sun ,  Kai Liu ,  Xiao Zhang ,  Yueh Ho ,  Leeshawn Luo

发明人： Ming Sun ,  Kai Liu ,  Xiao Zhang ,  Yueh Ho ,  Leeshawn Luo

IPC分类号： H01L23/02

CPC分类号： H01L23/49562 ,  H01L21/6835 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/36 ,  H01L24/39 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68354 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01065 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/37099 ,  H01L2924/206

摘要： This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

公开(公告)号：US09337132B2

公开(公告)日：2016-05-10

申请号：US14052711

申请日：2013-10-12

申请人： Ming Sun ,  Kai Liu ,  Xiaotian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

发明人： Ming Sun ,  Kai Liu ,  Xiaotian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

IPC分类号： H01L23/495 ,  H01L29/78 ,  H01L23/00 ,  H01L29/66 ,  H01L23/492

CPC分类号： H01L23/49562 ,  H01L23/492 ,  H01L23/4928 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/97 ,  H01L29/66477 ,  H01L29/78 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/014

摘要： A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

摘要翻译： 用于容纳，保护和提供用于功率晶体管的电触头的功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。 功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。 功率晶体管具有附接到顶部引线框架的底部漏极接触。 顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。 在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。

公开(公告)号：US20110227205A1

公开(公告)日：2011-09-22

申请号：US12726892

申请日：2010-03-18

申请人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

发明人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

IPC分类号： H01L23/52 ,  H01L21/60 ,  H01L23/538

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73263 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

摘要翻译： 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。

公开(公告)号：US07811904B2

公开(公告)日：2010-10-12

申请号：US11701561

申请日：2007-01-31

申请人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

发明人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/288 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

摘要翻译： 公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。 该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形 保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取 从保护胶带上取下模具。

公开(公告)号：US20100032819A1

公开(公告)日：2010-02-11

申请号：US12188160

申请日：2008-08-07

申请人： Kai Liu ,  Ming Sun

发明人： Kai Liu ,  Ming Sun

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/37099

摘要： A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas. Consequently, the semiconductor package reduces the inter-die distance from an otherwise direct transverse circuit routing between the longitudinal edges of the dies.

公开(公告)号：US07659191B2

公开(公告)日：2010-02-09

申请号：US11605831

申请日：2006-11-27

申请人： Kai Liu ,  Ming Sun

发明人： Kai Liu ,  Ming Sun

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/30 ,  H01L21/46 ,  H01L21/44

CPC分类号： H01L24/33 ,  H01L23/49582 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32506 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/01014 ,  H01L2924/00

摘要： A direct gold/silicon eutectic die bonding method is disclosed. The method includes the steps of gold plating a die bonding pad, grinding a wafer to a desired thickness, dicing the wafer after the grinding step, picking a die, and attaching the die to the die bonding pad at a temperature above the gold/silicon eutectic temperature. For thinner wafers, a dicing before grinding process is employed.

摘要翻译： 公开了一种直接的金/硅共晶裸片接合方法。 该方法包括以下步骤：将晶片接合焊盘镀金，将晶片研磨至所需厚度，在研磨步骤之后切割晶片，挑选模具，以及在高于金/硅的温度下将模具附接至芯片焊盘 共晶温度。 对于较薄的晶片，采用在研磨过程之前的切割。

公开(公告)号：US20090233403A1

公开(公告)日：2009-09-17

申请号：US12474089

申请日：2009-05-28

申请人： Kai Liu ,  Xiaotian Zhang ,  Ming Sun ,  Leeshawn Luo

发明人： Kai Liu ,  Xiaotian Zhang ,  Ming Sun ,  Leeshawn Luo

IPC分类号： H01L21/60

CPC分类号： H01L24/48 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.

摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极 键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

公开(公告)号：US07394151B2

公开(公告)日：2008-07-01

申请号：US11058913

申请日：2005-02-15

申请人： Leeshawn Luo ,  Kai Liu ,  Ming Sun ,  Xiao Tian Zhang

发明人： Leeshawn Luo ,  Kai Liu ,  Ming Sun ,  Xiao Tian Zhang

IPC分类号： H01L23/48

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49524 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

公开(公告)号：US20070231954A1

公开(公告)日：2007-10-04

申请号：US11396404

申请日：2006-03-31

申请人： Kai Liu ,  Ming Sun

发明人： Kai Liu ,  Ming Sun

IPC分类号： H01L21/00

CPC分类号： H01L24/27 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32506 ,  H01L2224/83801 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/01014 ,  H01L2924/00

摘要： A gold/silicon eutectic die bonding method is disclosed. The method includes the steps of 1) vacuum evaporating a layer of titanium to a silicon wafer backside, the titanium layer having a thickness less than 200 Å, 2) immediately vacuum evaporating a layer of gold onto the titanium layer, the gold layer having a thickness in the range of 0.5 to 1.5 microns, 3) dicing the wafer, and 4) mounting the die onto a substrate at a eutectic temperature to form a gold/silicon eutectic alloy bond.

摘要翻译： 公开了一种金/硅共晶晶片接合方法。 该方法包括以下步骤：1）将钛层真空蒸发到硅晶片背面，钛层的厚度小于200; 2）立即将一层金层真空蒸发到钛层上，金层具有 厚度在0.5至1.5微米的范围内，3）切割晶片，以及4）以共晶温度将模具安装在基板上以形成金/硅共晶合金。