公开(公告)号：US20140167212A1

公开(公告)日：2014-06-19

申请号：US13712980

申请日：2012-12-13

申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US08698196B2

公开(公告)日：2014-04-15

申请号：US13170965

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC分类号： H01L29/66 ,  H01L29/06

CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

公开(公告)号：US08643135B2

公开(公告)日：2014-02-04

申请号：US13134163

申请日：2011-05-31

申请人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

发明人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/407 ,  H01L29/0661 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在半导体衬底中并且具有有源电池区域和边缘终止区域，其中边缘终端区域包括填充有场强拥挤减少填充物的宽沟槽和埋在顶表面下方的掩埋场板 并且横向延伸超过场域拥挤场的顶部以使峰值电场横向移动到有源电池区域。 在一个具体的实施例中，场地拥挤减少填料包括填充在宽沟槽中的氧化硅。

公开(公告)号：US08581376B2

公开(公告)日：2013-11-12

申请号：US12819111

申请日：2010-06-18

申请人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

发明人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC分类号： H01L21/44 ,  H01L21/31

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US20130277740A1

公开(公告)日：2013-10-24

申请号：US13923065

申请日：2013-06-20

申请人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

发明人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

IPC分类号： H01L29/78

CPC分类号： H01L29/7823 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/47 ,  H01L29/7811

摘要： A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.

摘要翻译： 公开了一种用于布置设计和超级结装置制造的超结装置和方法。 可以配置活性单元列结构的布局，使得由于第一导电型掺杂剂引起的电荷由于活性单元区域中的掺杂层中的第二导电类型掺杂物而平衡电荷。 靠近端子列结构的活性单元列结构的端部的布局可以被配置为使得由于端部中的第一导电类型掺杂物引起的电荷和由端接塔结构中的第一导电类型掺杂剂引起的电荷平衡 在终端柱结构和端部之间的掺杂层的一部分中的第二导电类型掺杂剂引起的电荷。

公开(公告)号：US20130260522A1

公开(公告)日：2013-10-03

申请号：US13900162

申请日：2013-05-22

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7802 ,  H01L29/7811

摘要： A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

摘要翻译： 交错列超结半导体器件可以包括具有一个或多个器件单元的单元区域。 单元区域中的一个或多个器件单元包括被配置为用作漏极的半导体衬底和形成在衬底上的半导体层。 第一掺杂柱可以在半导体层中形成为第一深度，并且第二掺杂柱可以形成在半导体层中至第二深度。 第一个深度大于第二个深度。 第一和第二列掺杂有相同第二导电类型的掺杂剂并且沿着半导体层的厚度的一部分延伸并且由半导体层的一部分分离。

公开(公告)号：US20130049102A1

公开(公告)日：2013-02-28

申请号：US13199381

申请日：2011-08-25

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

摘要翻译： 本发明公开了一种形成在半导体衬底中的半导体功率器件，包括在轻掺杂区域顶部附近的半导体衬底的顶表面附近的高掺杂区域。 半导体功率器件还包括设置在半导体衬底的顶表面附近的体区，源区和栅极以及设置在半导体衬底的底表面处的漏极。 半导体功率器件还包括开口到高掺杂区域的源沟槽，填充有与顶表面附近的源区电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域具有相反导电性的掺杂剂的掩埋场环区域。 在替代实施例中，半导体功率器件还包括围绕源极沟槽的侧壁的掺杂区域，并掺杂有相同导电类型的掩埋场环区域的掺杂剂，用作电荷供应路径。

公开(公告)号：US08373208B2

公开(公告)日：2013-02-12

申请号：US12799810

申请日：2010-04-30

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8232

CPC分类号： H01L29/808 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66696 ,  H01L29/66901 ,  H01L29/7817 ,  H01L29/7821

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

摘要翻译： 横向超结JFET由负载在N +衬底上的P表面层上的堆叠的交替P型和N型半导体层形成。 N +漏极柱向下延伸穿过超结结构和P-epi以连接到N +衬底以使器件成为底部漏极器件。 N +源极柱和P +栅极柱延伸穿过超级结，但在P-epi层处停止。 栅极 - 漏极雪崩钳位二极管从P +栅极底部通过P-epi到N +漏极衬底形成。

公开(公告)号：US08362547B2

公开(公告)日：2013-01-29

申请号：US12005166

申请日：2007-12-21

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/8725

摘要： A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body into the drain region; an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain region form a Schottky diode; and a Schottky barrier controlling layer.

摘要翻译： 形成在半导体衬底上的半导体器件包括：覆盖半导体衬底的外延层; 在半导体衬底背面形成的漏极; 漏极区域，其延伸到所述外延层中; 和活跃区域。 有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区域接触沟槽，其延伸穿过所述源极和所述本体进入所述漏极区域; 有源区接触电极，设置在有源区接触沟槽内，其中有源区接触电极和漏区形成肖特基二极管; 和肖特基势垒控制层。

公开(公告)号：US20130001694A1

公开(公告)日：2013-01-03

申请号：US13170965

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC分类号： H01L23/60 ,  H01L21/336

CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

摘要翻译： 具有降低的钳位电压的低电容瞬态电压抑制器包括n +型衬底，衬底上的第一外延层，形成在第一外延层内的掩埋层，在第一外延层上形成的第二外延层，以及在第一外延层上形成的注入层 掩埋层下面的第一个外延层。 植入层延伸超过掩埋层。 第一沟槽位于掩埋层的边缘和植入层的边缘。 第二沟槽位于掩埋层的另一边缘并延伸到植入层中。 第三沟槽位于植入层的另一边缘。 每个沟槽衬有介电层。 一组源区形成在第二外延层的顶表面内。 沟渠和源区交替出现。 在第二外延层中形成一对注入区。