公开(公告)号：US20160365346A1

公开(公告)日：2016-12-15

申请号：US14735984

申请日：2015-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。

公开(公告)号：US20160254361A1

公开(公告)日：2016-09-01

申请号：US15154495

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/45 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US09337317B2

公开(公告)日：2016-05-10

申请号：US14697670

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/28 ,  H01L21/266 ,  H01L29/78 ,  H01L27/06 ,  H01L29/861 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/823431 ,  H01L27/0629 ,  H01L29/6609 ,  H01L29/66128 ,  H01L29/785 ,  H01L29/8611

Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.

公开(公告)号：US20160020335A1

公开(公告)日：2016-01-21

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/808 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20150140698A1

公开(公告)日：2015-05-21

申请号：US14607161

申请日：2015-01-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

公开(公告)号：US20150140697A1

公开(公告)日：2015-05-21

申请号：US14607160

申请日：2015-01-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定 如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

公开(公告)号：US10833019B2

公开(公告)日：2020-11-10

申请号：US16668409

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L23/485 ,  H01L21/285 ,  H01L29/66

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

公开(公告)号：US10749038B2

公开(公告)日：2020-08-18

申请号：US16057579

申请日：2018-08-07

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

公开(公告)号：US10439031B2

公开(公告)日：2019-10-08

申请号：US15338925

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L23/525 ,  H01L27/112 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.

公开(公告)号：US10388754B2

公开(公告)日：2019-08-20

申请号：US15343776

申请日：2016-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.