公开(公告)号：US09214432B2

公开(公告)日：2015-12-15

申请号：US14499737

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Guido Boenig ,  Olaf Hohlfeld

IPC: H01L23/00 ,  H01L23/24 ,  H01L23/053 ,  H01L23/16

CPC classification number: H01L23/564 ,  H01L23/053 ,  H01L23/16 ,  H01L23/24 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48096 ,  H01L2224/48105 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4909 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module has a carrier, a semiconductor chip mounted on the carrier, a bond wire, a module housing, and a first sound absorber. The module housing has a housing side wall. The bond wire is arranged in the module housing. At least a section of the first sound absorber is arranged between the semiconductor chip and the housing side wall.

Abstract translation: 半导体模块具有载体，安装在载体上的半导体芯片，接合线，模块壳体和第一吸音体。 模块外壳具有外壳侧壁。 接合线布置在模块外壳中。 第一吸声器的至少一部分布置在半导体芯片和壳体侧壁之间。

公开(公告)号：US20150287698A1

公开(公告)日：2015-10-08

申请号：US14669208

申请日：2015-03-26

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld

IPC: H01L25/065 ,  H01L23/10 ,  H01L23/492 ,  H01L23/04 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L23/04 ,  H01L23/051 ,  H01L23/10 ,  H01L23/3142 ,  H01L23/48 ,  H01L23/492 ,  H01L24/96 ,  H01L25/07 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor assembly includes a frame having at least one opening, an identical number of electrically conductive first contact plates, and an identical number of chip arrays. Each chip array has a number of semiconductor chips that are cohesively connected to one another by an embedding compound. In addition, each of the semiconductor chips has a first load terminal and a second load terminal arranged at mutually opposite sides of the relevant semiconductor chip. One of the chip arrays is inserted into each of the openings. Each of the first contact plates is arranged above one of the chip arrays in such a way that, for each of the semiconductor chips, the first load terminal is situated at a side of said semiconductor chip facing the first contact plate and the second load terminal is situated a of said semiconductor chip facing away from the first contact plate.

Abstract translation: 半导体组件包括具有至少一个开口，相同数量的导电第一接触板和相同数量的芯片阵列的框架。 每个芯片阵列具有通过嵌入化合物彼此内聚连接的多个半导体芯片。 此外，每个半导体芯片具有布置在相关半导体芯片的相对的相对侧的第一负载端子和第二负载端子。 其中一个芯片阵列插入到每个开口中。 每个第一接触板被布置在一个芯片阵列之上，使得对于每个半导体芯片，第一负载端子位于面向第一接触板的第一半导体芯片的一侧和第二负载端子 位于所述半导体芯片的背离第一接触板的一侧。

公开(公告)号：US08981545B2

公开(公告)日：2015-03-17

申请号：US13932531

申请日：2013-07-01

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Uwe Jansen

IPC: H01L23/16 ,  H01L23/24 ,  H01L23/00 ,  H01L25/18 ,  H01L23/29

CPC classification number: H01L23/24 ,  H01L23/291 ,  H01L23/58 ,  H01L24/42 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module includes an electrically conductive lower contact piece and an electrically conductive upper contact piece spaced apart from one another in a vertical direction. The module further includes a semiconductor chip having a first load connection and a second load connection. The semiconductor chip is electrically conductively connected by the second load connection to the lower contact piece, and electrically conductively connected to the upper contact piece by at least one bonding wire bonded to the first load connection. An explosion protection means is arranged between the first load connection and the upper contact piece and into which each of the bonding wires is embedded over at least 80% or over at least 90% of its length.

Abstract translation: 半导体模块包括导电下接触片和在垂直方向上彼此间隔开的导电上接触片。 该模块还包括具有第一负载连接和第二负载连接的半导体芯片。 半导体芯片通过第二负载连接导电连接到下接触片，并且通过至少一个接合到第一负载连接的接合线而导电地连接到上接触片。 防爆装置设置在第一负载连接件和上接触片之间，每个接合线在其长度至少80％或以上至少80％的范围内被嵌入其中。

公开(公告)号：US20150061100A1

公开(公告)日：2015-03-05

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/492 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

Abstract translation: 半导体装置包括顶部和底部接触板，多个芯片组件，电介质嵌入化合物和控制电极互连结构。 每个芯片组件具有半导体芯片，该半导体芯片具有半导体本体。 半导体本体具有顶侧和相对的下侧。 顶侧在垂直方向上与下侧隔开。 每个半导体芯片具有布置在顶侧的顶部主电极，设置在下侧的底部主电极，布置在顶侧的控制电极和布置在顶部主电极对面侧的导电顶部补偿裸片 远离半导体本体并且通过顶部连接层内导电地连接到顶部主电极。 可以通过控制电极来控制顶部主电极和底部主电极之间的电流。

公开(公告)号：US11978700B2

公开(公告)日：2024-05-07

申请号：US17872255

申请日：2022-07-25

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/24 ,  H01L23/31 ,  H01L23/367 ,  H01L23/40 ,  H01L23/498 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L23/49861 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3672 ,  H01L23/4006 ,  H01L23/49844 ,  H01L25/072 ,  H01L23/564 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.

公开(公告)号：US20210335682A1

公开(公告)日：2021-10-28

申请号：US17366870

申请日：2021-07-02

Applicant: Infineon Technologies AG

Inventor： Alexander Roth ,  Olaf Hohlfeld

IPC: H01L23/24 ,  H01L23/053 ,  H01L21/56 ,  H01L23/29

Abstract: A method is disclosed for producing a power semiconductor module that includes a substrate, at least one semiconductor body, a connecting element and a contact element. The method includes: arranging the substrate in a housing having walls; at least partly filling a capacity formed by the walls of the housing and the substrate with an encapsulation material; hardening the encapsulation material to form a hard encapsulation; and closing the housing, wherein the contact element extends from the connecting element through an interior of the housing and through an opening in a cover of the housing to an outside of the housing in a direction perpendicular to a first surface of a first metallization layer of the substrate.

公开(公告)号：US20200266171A1

公开(公告)日：2020-08-20

申请号：US16792682

申请日：2020-02-17

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld

IPC: H01L23/00 ,  H01L27/12

Abstract: A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

公开(公告)号：US20190237372A1

公开(公告)日：2019-08-01

申请号：US16260834

申请日：2019-01-29

Applicant: Infineon Technologies AG

Inventor： Alexander Roth ,  Olaf Hohlfeld

IPC: H01L23/24 ,  H01L23/053 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L23/24 ,  H01L21/54 ,  H01L21/56 ,  H01L23/053 ,  H01L23/295 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A power semiconductor module arrangement includes a substrate arranged in a housing. The substrate includes a first metallization layer arranged on a first side of a dielectric insulation layer and a second metallization layer arranged on a second side of the dielectric insulation layer. At least one semiconductor body is mounted on a first surface of the first metallization layer facing away from the dielectric insulation layer. A connecting element is arranged on and electrically connected to the first surface. A contact element is inserted into and electrically connected to the connecting element, and extends from the connecting element through an interior of the housing and through an opening in the cover of the housing to an outside of the housing in a direction perpendicular to the first surface. A hard encapsulation is arranged adjacent to the first metallization layer and at least partly fills the inside of the housing.

公开(公告)号：US20190189553A1

公开(公告)日：2019-06-20

申请号：US16220956

申请日：2018-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/40 ,  H01L23/31 ,  H01L23/24

CPC classification number: H01L23/49861 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3672 ,  H01L23/4006 ,  H01L23/49844 ,  H01L23/564 ,  H01L25/072 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: A power semiconductor module arrangement including two or more individual semiconductor devices each semiconductor device having a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. The power semiconductor module arrangement further includes a frame surrounding the two or more individual semiconductor devices, and a casting compound at least partly filling a capacity within the frame, thereby at least partly enclosing the two or more individual semiconductor devices.

公开(公告)号：US10242969B2

公开(公告)日：2019-03-26

申请号：US14077696

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Angela Kessler ,  Magdalena Hoier

IPC: H01L25/07 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L21/56 ,  H01L23/373 ,  H01L23/433 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.