公开(公告)号：US10031868B2

公开(公告)日：2018-07-24

申请号：US15608846

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  James A. McCall ,  Bryan K. Casper

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F11/10

CPC classification number: G06F13/1657 ,  G06F11/10 ,  G06F13/4004 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4217 ,  G06F13/4221 ,  G06F13/4234 ,  H04L25/4915 ,  Y02D10/14 ,  Y02D10/151

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

公开(公告)号：US09998125B2

公开(公告)日：2018-06-12

申请号：US15025226

申请日：2013-11-19

Applicant: Intel Corporation

Inventor： Ganesh Balamurugan ,  Mozhgan Mansuri ,  Sami Hyvonen ,  Bryan K. Casper ,  Frank O'Mahony

IPC: H03L7/00 ,  G11C7/22 ,  H03K5/156 ,  H04L25/03 ,  H04B1/04 ,  G11C7/10

CPC classification number: H03L7/00 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/08 ,  H04B1/04 ,  H04L25/03

Abstract: Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.

公开(公告)号：US09582454B2

公开(公告)日：2017-02-28

申请号：US14218684

申请日：2014-03-18

Applicant: Intel Corporation

Inventor： Tzu-Chien Hsueh ,  Ganesh Balamurugan ,  Bryan K. Casper

IPC: G06F13/40 ,  G06F1/18 ,  G06F13/20 ,  G06F13/42

CPC classification number: G06F13/4072 ,  G06F1/189 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/20 ,  G06F13/36 ,  G06F13/4282 ,  H04L25/0272

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

Abstract translation: 描述的是可重新配置的发射机，其包括：第一焊盘; 第二垫 耦合到第一焊盘的第一单端驱动器; 第二个单端驱动器到第二个垫; 耦合到所述第一和第二焊盘的差分驱动器; 以及用于启用第一和第二单端驱动器或启用差分驱动器的逻辑单元。

公开(公告)号：US20160285513A1

公开(公告)日：2016-09-29

申请号：US14668199

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Shreyas Sen ,  Chintan S. Thakkar ,  Bryan K. Casper ,  James E. Jaussi

IPC: H04B5/00 ,  H04W76/04 ,  H01P3/16

CPC classification number: H04B5/0012 ,  H01P3/16 ,  H01Q13/24 ,  H04B5/0031

Abstract: Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package with a central processing unit (CPU) circuit, an input-output (I/O) circuit coupled with the CPU circuit, and a dielectric electromagnetic waveguide coupled with the I/O circuit, to enable communications between the CPU circuit and another apparatus. In another instance, the apparatus may include a plurality of coupler pads disposed on a first surface of the apparatus; and a processor electrically coupled with the coupler pads. One of the coupler pads may form capacitive coupling with one of coupler pads disposed on a second surface of another apparatus, in response to a placement of the first surface in at least partial contact with the second surface, to enable proximity data communication between the processor and the other apparatus. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供用于邻近通信的装置和系统。 该装置可以包括具有中央处理单元（CPU）电路，与CPU电路耦合的输入输出（I / O）电路和与I / O电路耦合的介电电磁波导的集成电路（IC）封装， 以实现CPU电路和另一装置之间的通信。 在另一种情况下，该设备可以包括设置在设备的第一表面上的多个耦合器焊盘; 以及与耦合器焊盘电耦合的处理器。 响应于第一表面与第二表面至少部分接触的布置，耦合器中的一个可以与设置在另一装置的第二表面上的耦合器焊盘之一形成电容耦合，以使处理器之间的接近数据通信 和另一台设备。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160277219A1

公开(公告)日：2016-09-22

申请号：US14660799

申请日：2015-03-17

Applicant: Intel Corporation

Inventor： Hariprasath Venkatram ,  Sami Hyvonen ,  Tawfiq Musah ,  Bryan K. Casper

IPC: H04L25/03 ,  H04L7/033

CPC classification number: H04L25/03057 ,  H04L7/0062 ,  H04L7/033 ,  H04L7/0334 ,  H04L25/03878

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract translation: 描述了一种装置，包括：放大器; 第一组采样器，用于根据时钟信号对从放大器输出的数据进行采样，该采样器组用于产生输出; 以及将第一组采样器的输出转换为1 -hot编码数据的转换器。

公开(公告)号：US20160261435A1

公开(公告)日：2016-09-08

申请号：US14637291

申请日：2015-03-03

Applicant: INTEL CORPORATION

Inventor： Tawfiq Musah ,  Hariprasath Venkatram ,  Bryan K. Casper

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L7/0062 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Abstract translation: 描述了一种装置，其包括：可变增益放大器（VGA）; 一组采样器，用于根据时钟信号对从VGA输出的数据进行采样; 以及时钟数据恢复（CDR）电路，用于调整时钟信号的相位，使得与采样数据相关联的第一后置光标信号的大小基本上是与采样数据相关联的主光标抽头的幅度的一半。

公开(公告)号：US20160182259A1

公开(公告)日：2016-06-23

申请号：US14573343

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Tawfiq Musah ,  Gokce Keskin ,  Ganesh Balamurugan ,  James E. Jaussi ,  Bryan K. Casper

IPC: H04L25/03 ,  H04L7/02

CPC classification number: H04L25/03057 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03146 ,  H04L25/14

Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

Abstract translation: 一些实施例包括具有用于接收输入信号的输入的装置和方法，用于接收具有不同相位以对输入信号进行采样的时钟信号的附加输入以及具有DFE切片的判决反馈均衡器（DFE）。 DFE片包括多个数据比较器，用于基于输入信号的采样来提供数据信息，以及多个相位误差比较器，以提供与输入信号的采样相关联的相位误差信息。 DFE切片的相位误差比较器的数量不大于DFE切片的数据比较器的数量。