公开(公告)号：US11271010B2

公开(公告)日：2022-03-08

申请号：US16629802

申请日：2017-09-20

申请人： Intel Corporation

发明人： Ranjith Kumar ,  Quan Shi ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sourav Chakravarty ,  Barbara A. Chappell ,  M. Clair Webb

IPC分类号： H01L27/118 ,  G06F30/392 ,  H01L27/02 ,  H01L27/092

摘要： Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US11127712B2

公开(公告)日：2021-09-21

申请号：US15857731

申请日：2017-12-29

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Mark T. Bohr ,  Udi Sherel ,  Leonard M. Neiberg ,  Nevine Nassif ,  Wesley D. McCullough

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L25/00

摘要： Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

公开(公告)号：US11043459B2

公开(公告)日：2021-06-22

申请号：US16611129

申请日：2017-06-29

申请人： INTEL CORPORATION

发明人： Edward A. Burton ,  Mark T. Bohr ,  Murray Fitzpatrick Kelley ,  Shawn Michael Klauser

IPC分类号： H01L23/544 ,  H01L23/538 ,  G03F7/20

摘要： Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.

公开(公告)号：US10886217B2

公开(公告)日：2021-01-05

申请号：US16348116

申请日：2016-12-23

申请人： Intel Corporation

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L21/306 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

摘要： Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

公开(公告)号：US20180096891A1

公开(公告)日：2018-04-05

申请号：US15827491

申请日：2017-11-30

申请人： INTEL CORPORATION

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/423 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/45 ,  H01L29/16 ,  H01L29/08 ,  H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/285

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US09892967B2

公开(公告)日：2018-02-13

申请号：US15299106

申请日：2016-10-20

申请人： INTEL CORPORATION

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/16 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/08 ,  H01L23/522 ,  H01L21/283 ,  H01L29/78 ,  H01L29/49

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20160247727A1

公开(公告)日：2016-08-25

申请号：US15141777

申请日：2016-04-28

申请人： Intel Corporation

发明人： Mark T. Bohr

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51

CPC分类号： H01L21/823814 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11807 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

公开(公告)号：US09337336B2

公开(公告)日：2016-05-10

申请号：US14882434

申请日：2015-10-13

申请人： Intel Corporation

发明人： Mark T. Bohr

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/82 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11807 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

摘要翻译： 本发明的一些实施例包括与NMOS和PMOS晶体管应变相关的装置和方法。

公开(公告)号：US12074138B2

公开(公告)日：2024-08-27

申请号：US18378978

申请日：2023-10-11

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

摘要： Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US11996362B2

公开(公告)日：2024-05-28

申请号：US17493715

申请日：2021-10-04

申请人： Intel Corporation

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC分类号： H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/30604 ,  H01L21/768 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/785 ,  H01L29/7851

摘要： Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.