公开(公告)号：US20170235678A1

公开(公告)日：2017-08-17

申请号：US15362820

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/1036 ,  G06F12/0891 ,  G06F9/455 ,  G06F12/123 ,  G06F12/109 ,  G06F12/1045 ,  G06F12/0804

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US09507730B2

公开(公告)日：2016-11-29

申请号：US14858835

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/10 ,  G06F9/48 ,  G06F9/455 ,  G06F12/02 ,  G06F12/12

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US09423959B2

公开(公告)日：2016-08-23

申请号：US13931875

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Richard A. Uhlig ,  Robert S. Chappell ,  Joseph Nuzman ,  Kai Cheng ,  Sailesh Kottapalli ,  Yen-Cheng Liu ,  Mohan Kumar ,  Raj K. Ramanujan ,  Glenn J. Hinton

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

Abstract translation: 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

公开(公告)号：US09262338B1

公开(公告)日：2016-02-16

申请号：US14675292

申请日：2015-03-31

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09235434B2

公开(公告)日：2016-01-12

申请号：US13837526

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Dion Rodgers ,  Richard A. Uhlig ,  Lawrence O. Smith ,  Barry E. Huntley

IPC: G06F9/455 ,  G06F9/54 ,  G06F13/24 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/45533 ,  G06F9/3861 ,  G06F9/45545 ,  G06F9/4555 ,  G06F9/45558 ,  G06F9/4812 ,  G06F9/542 ,  G06F13/24 ,  G06F2009/45566

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

公开(公告)号：US09152561B2

公开(公告)日：2015-10-06

申请号：US14579040

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F9/48 ,  G06F12/10 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US11829789B2

公开(公告)日：2023-11-28

申请号：US17671093

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Ashok Sunder Rajan ,  Richard A. Uhlig ,  Rajendra S. Yavatkar ,  Tsung-Yuan C. Tai ,  Christian Maciocco ,  Jeffrey R. Jackson ,  Daniel J. Dahle

IPC: G06F9/455 ,  G06F9/50 ,  H04L41/00 ,  G06F9/445

CPC classification number: G06F9/45533 ,  G06F9/455 ,  G06F9/45537 ,  G06F9/5077 ,  H04L41/00 ,  G06F9/445

Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.

公开(公告)号：US10599547B2

公开(公告)日：2020-03-24

申请号：US15827890

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Andrew V. Anderson ,  Richard A. Uhlig ,  David M. Durham ,  Ronak Singhal ,  Xiangbin Wu ,  Sailesh Kottapalli

IPC: G06F11/34 ,  G06F9/455 ,  G06F11/30 ,  G06F13/24

Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.

公开(公告)号：US20180357179A1

公开(公告)日：2018-12-13

申请号：US16005385

申请日：2018-06-11

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/1036 ,  G06F9/455 ,  G06F9/48 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F12/1027

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US20180225136A1

公开(公告)日：2018-08-09

申请号：US15812888

申请日：2017-11-14

Applicant: INTEL CORPORATION

Inventor： Ashok Sunder Rajan ,  Richard A. Uhlig ,  Rajendra S. Yavatkar ,  Tsung-Yuan C. Tai ,  Christian Maciocco ,  Jeffrey R. Jackson ,  Daniel J. Dahle

IPC: G06F9/455 ,  H04L12/24 ,  G06F9/50 ,  G06F9/445

Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.