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    Synchronization and order detection in a memory system
    31.
    发明授权
    Synchronization and order detection in a memory system 有权
    存储系统中的同步和顺序检测

    公开(公告)号：US09594647B2

    公开(公告)日：2017-03-14

    申请号：US15262111

    申请日：2016-09-12

    Applicant: International Business Machines Corporation

    Inventor： Patrick J. Meaney ,  Glenn D. Gilda ,  Eric E. Retter ,  John S. Dodson ,  Gary A. Van Huben ,  Brad W. Michael ,  Stephen J. Powell

    IPC: G06F11/16 ,  G06F1/12 ,  G11C11/4076 ,  G11C11/4093 ,  G06F1/10 ,  G06F1/04

    CPC classification number: G06F11/1679 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F1/32 ,  G06F11/1497 ,  G06F11/1604 ,  G06F11/1675 ,  G06F13/1689 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52

    Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

    Abstract translation: 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。

    EARLY DATA DELIVERY PRIOR TO ERROR DETECTION COMPLETION
    35.
    发明申请
    EARLY DATA DELIVERY PRIOR TO ERROR DETECTION COMPLETION 有权
    在错误检测完成前的早期数据传送

    公开(公告)号：US20150019935A1

    公开(公告)日：2015-01-15

    申请号：US14501101

    申请日：2014-09-30

    Applicant: International Business Machines Corporation

    Inventor： Glenn D. Gilda ,  Mark R. Hodges ,  Vesselina K. Papazova ,  Patrick J. Meaney

    IPC: G06F11/10

    CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F11/08

    Abstract: A computer implemented method for early data delivery prior to error detection completion in a memory system includes receiving a frame of a multi-frame data block at a memory control unit interface. A controller writes the frame to a buffer control block in a memory controller nest domain. The frame is read from the buffer control block by a cache subsystem interface in a system domain prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame by an error detector in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to a correction pipeline in the system domain. The intercept signal indicates that error correction is needed prior to writing data in the frame to a cache subsystem.

    Abstract translation: 在存储器系统中的错误检测完成之前的用于早期数据传送的计算机实现方法包括在存储器控制单元接口处接收多帧数据块的帧。 控制器将帧写入存储器控制器嵌套域中的缓冲器控制块。 在完成多帧数据块的错误检测之前，通过系统域中的缓存子系统接口从缓冲器控制块读取该帧。 通过存储器控制器嵌套域中的错误检测器在帧上执行错误检测。 基于检测到帧中的错误，拦截信号从存储器控制器嵌套域发送到系统域中的校正流水线。 截距信号表示在将帧中的数据写入缓存子系统之前需要纠错。

    FIRST-IN-FIRST-OUT QUEUE-BASED COMMAND SPREADING
    36.
    发明申请
    FIRST-IN-FIRST-OUT QUEUE-BASED COMMAND SPREADING 有权
    一流的基于QUEUE的命令扩展

    公开(公告)号：US20140281042A1

    公开(公告)日：2014-09-18

    申请号：US13835205

    申请日：2013-03-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Mark R. Hodges ,  Vesselina K. Papazova ,  Patrick J. Meaney

    IPC: G06F3/06

    CPC classification number: G06F13/1642 ,  Y02D10/14

    Abstract: Embodiments relate to first-in-first-out (FIFO) queue based command spreading. An aspect includes receiving a plurality of commands by a first level priority stage of a memory control unit (MCU), wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip. Another aspect includes storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip. Another aspect includes selecting a FIFO queue of the plurality of FIFO queues and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage. Another aspect includes a third level priority on the buffer chip associated with each respective FIFO queue to help optimize the bandwidth on the returning upstream fetch bus.

    Abstract translation: 实施例涉及先进先出（FIFO）队列的命令扩展。 一个方面包括通过存储器控制单元（MCU）的第一级优先级接收多个命令，其中多个命令中的每一个与位于缓冲器芯片上的多个端口中的一个相关联。 另一方面包括将多个命令中的每一个存储在MCU中的多个FIFO队列的FIFO队列中，其中多个命令中的每一个基于命令的相关端口被分配给FIFO队列，并且多个 FIFO队列与位于缓冲器芯片上的多个端口中的相应一个端口相关联。 另一方面包括选择多个FIFO队列中的FIFO队列，并通过第二级优先级将来自所选FIFO队列的命令转发到缓冲器芯片。 另一方面包括与每个相应FIFO队列相关联的缓冲器芯片的第三级优先级，以帮助优化返回的上行获取总线上的带宽。

    DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS
    37.
    发明申请
    DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS 有权
    独立存储器（RAIM）系统的冗余阵列中的动态分级存储器件保护

    公开(公告)号：US20140101518A1

    公开(公告)日：2014-04-10

    申请号：US14102579

    申请日：2013-12-11

    Applicant: International Business Machines Corporation

    Inventor： Patrick J. Meaney ,  William J. Clarke ,  Eldee Stephens ,  Judy S. Johnson

    IPC: G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1004 ,  G06F11/1076 ,  G06F2211/109

    Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.

    Abstract translation: 提供了包括多个存储器件的独立存储器（RAIM）系统的冗余阵列中的动态分级存储器件保护。 确定多个存储器件中的第一故障存储器件的第一严重性级别。 第一故障存储设备与用于将第一故障存储设备的位置传送到纠错码（ECC）的标识符相关联。 确定多个存储器件中的第二故障存储器件的第二严重性级别。 确定第二严重性级别高于第一严重性级别。 基于确定第二严重性级别高于第一严重性级别，去除来自第一故障存储器设备的标识符。 基于确定第二严重性级别高于第一严重性级别，将标识符应用于第二故障存储设备。

    Collecting failure information on error correction code (ECC) protected data
    38.
    发明授权
    Collecting failure information on error correction code (ECC) protected data 有权
    收集有关纠错码（ECC）保护数据的故障信息

    公开(公告)号：US08423875B2

    公开(公告)日：2013-04-16

    申请号：US13648555

    申请日：2012-10-10

    Applicant: International Business Machines Corporation

    Inventor： Arthur J. O'Neill ,  Patrick J. Meaney

    IPC: H03M13/00 ,  G11C29/00

    CPC classification number: G06F11/10

    Abstract: Methods and apparatus for error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

    Abstract translation: 用于纠错码（ECC）调试的方法和装置可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。 该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。 该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

    Reduced latency error correction decoding
    40.
    发明授权
    Reduced latency error correction decoding 有权

    公开(公告)号：US10601448B2

    公开(公告)日：2020-03-24

    申请号：US15830526

    申请日：2017-12-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Glenn Gilda ,  Patrick J. Meaney ,  Arthur O'Neill ,  Barry M. Trager

    IPC: H03M13/15 ,  H03M13/00

    Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.

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