公开(公告)号：US09954065B2

公开(公告)日：2018-04-24

申请号：US14936279

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Ingo Muri ,  Iris Moder ,  Johannes Baumgartl

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/1095 ,  H01L21/265 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3205 ,  H01L21/324 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66477 ,  H01L29/7397 ,  H01L29/78

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

公开(公告)号：US09608092B2

公开(公告)日：2017-03-28

申请号：US14822267

申请日：2015-08-10

Applicant: Infineon Technologies AG

Inventor： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC: H01L29/80 ,  H01L29/66 ,  H01L29/78 ,  H01L29/47 ,  H01L29/04 ,  H01L29/16 ,  H01L29/812 ,  H01L29/267 ,  H01L29/872

CPC classification number: H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

Abstract: A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.

公开(公告)号：US09571087B2

公开(公告)日：2017-02-14

申请号：US14963509

申请日：2015-12-09

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H01L29/739 ,  H01L29/732 ,  H03K17/12 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H03K3/01 ,  H03K17/66

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据一种方法的实施例，半导体器件在反向偏置单极模式下工作，然后在正向偏置模式中将半导体器件操作为截止状态。 半导体器件包括设置在器件的单元区域外的至少一个浮置寄生区域。

公开(公告)号：US09536958B2

公开(公告)日：2017-01-03

申请号：US14301995

申请日：2014-06-11

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Frank Pfirsch ,  Hans-Joerg Timme

IPC: H01L29/08 ,  H01L29/36 ,  H01L21/22 ,  H01L21/265 ,  H01L21/322 ,  H01L29/32 ,  H03H9/02 ,  H03H9/17

CPC classification number: H01L29/36 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/3225 ,  H01L29/32 ,  H03H9/02047 ,  H03H9/175

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm−3.

Abstract translation: 半导体衬底包括具有导带边缘和价带边缘的高电阻半导体材料，带隙由带隙分开，其中半导体材料包括受体或施主杂质原子或晶体缺陷，其能级位于至少120meV 导带边缘，以及带隙中的价带边缘; 并且其中杂质原子或晶体缺陷的浓度大于1×10 12 cm -3。

公开(公告)号：US09373710B2

公开(公告)日：2016-06-21

申请号：US14278519

申请日：2014-05-15

Applicant: Infineon Technologies AG

Inventor： Vera Van Treek ,  Frank Pfirsch ,  Roman Baburske ,  Franz-Josef Niedernostheide

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7397

Abstract: A semiconductor component is described herein. In accordance with one example of the invention, the semiconductor component includes a semiconductor body, which has a top surface and a bottom surface. A body region, which is doped with dopants of a second doping type, is arranged at the top surface of the semiconductor body. A drift region is arranged under the body region and doped with dopants of a first doping type, which is complementary to the second doping type. Thus a first pn-junction is formed at the transition between the body region and the drift region. A field stop region is arranged under the drift region and adjoins the drift region. The field stop region is doped with dopants of the same doping type as the drift region. However, the concentration of dopants in the field stop region is higher than the concentration of dopants in the drift region. At least one pair of semiconductor layers composed of a first and a second semiconductor layer are arranged in the drift region. The first semiconductor layer extends substantially parallel to the top surface of the semiconductor body and is doped with dopants of the first doping type but with a higher concentration of dopants than the drift region. The second semiconductor layer is arranged adjacent to or adjoining the first semiconductor layer and is doped with dopants of the second doping type. Furthermore, the second semiconductor layer is structured to include openings so that a vertical current path is provided through the drift region without an intervening pn-junction.

Abstract translation: 本文描述了半导体部件。 根据本发明的一个示例，半导体部件包括具有顶表面和底表面的半导体本体。 掺杂有第二掺杂类型的掺杂剂的体区设置在半导体本体的顶表面。 漂移区布置在体区下方并掺杂有与第二掺杂类型互补的第一掺杂类型的掺杂剂。 因此，在身体区域和漂移区域之间的过渡处形成第一pn结。 漂移区域下方设置场停止区域，并与漂移区域相邻。 场停止区域掺杂有与漂移区相同的掺杂类型的掺杂剂。 然而，场停止区域中的掺杂剂的浓度高于漂移区域中的掺杂剂的浓度。 在漂移区域中布置由第一和第二半导体层组成的至少一对半导体层。 第一半导体层基本上平行于半导体本体的顶表面延伸，并掺杂有第一掺杂类型的掺杂剂，但具有比漂移区更高的掺杂剂浓度。 第二半导体层被布置为与第一半导体层相邻或相邻，并且掺杂有第二掺杂类型的掺杂剂。 此外，第二半导体层被构造成包括开口，使得通过漂移区域提供垂直电流路径，而没有中间pn结。

公开(公告)号：US20160111508A1

公开(公告)日：2016-04-21

申请号：US14976526

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Christian Foerster ,  Georg Ehrentraut ,  Frank Pfirsch ,  Thomas Raker

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/4236 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.

公开(公告)号：US09231581B2

公开(公告)日：2016-01-05

申请号：US14551632

申请日：2014-11-24

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H01L29/66 ,  H01L29/739 ,  H03K17/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H03K3/01

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据一种方法的实施例，半导体器件在反向偏置单极模式下工作，然后在正向偏置模式中将半导体器件操作为截止状态。 半导体器件包括设置在器件的单元区域外的至少一个浮置寄生区域。

公开(公告)号：US20150279985A1

公开(公告)日：2015-10-01

申请号：US14228881

申请日：2014-03-28

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Johannes Georg Laven ,  Christian Jaeger ,  Frank Wolter ,  Frank Pfirsch ,  Antonio Vellei

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7841

Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.

Abstract translation: 晶体管器件包括在半导体主体中的第一和第二沟槽之间的半导体台面区域，半导体台面区域中的第一导电类型的主体区域和第二导电类型的源极区域，第二导电类型的漂移区域 所述半导体本体和与所述第一沟槽中的所述主体区域相邻的栅电极，并且通过栅极电介质与所述体区电介质绝缘。 体区域将源极区域与漂移区域分离并延伸到与源极区域相邻的半导体台面区域的表面。 身体区域包括邻接半导体台面区域和第一沟槽的表面的表面区域。 表面区域具有比将源极区域与漂移区域分开的体区域的部分更高的掺杂浓度。

公开(公告)号：US20150091053A1

公开(公告)日：2015-04-02

申请号：US14041094

申请日：2013-09-30

Applicant: Infineon Technologies AG

Inventor： Christian Philipp Sandow ,  Hans-Joachim Schulze ,  Johannes Georg Laven ,  Franz-Josef Niedernostheide ,  Frank Pfirsch ,  Hans-Peter Felsl

IPC: H01L29/739

CPC classification number: H01L29/1095 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397

Abstract: An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body region is arranged between the first emitter region and the base region. The base region is arranged between the body region and the second emitter region. The IGBT further includes a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a base electrode adjacent the base region and dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A doping concentration of the first base region section is higher than a doping concentration of the second base region section.

Abstract translation: IGBT包括至少一个第一类型晶体管单元，其包括基极区，第一发射区，体区和第二发射极区。 体区布置在第一发射区和基区之间。 基部区域布置在主体区域和第二发射区域之间。 IGBT还包括与主体区域相邻并且通过栅极电介质与体区电介绝缘的栅电极和与基极区域相邻并且与基极区域由基极电介质介电绝缘的基极。 基极区域具有邻接基极电介质的第一基极区域和布置在第二发射极区域与第一基极区域之间的第二基极区域区域。 第一基极区域的掺杂浓度高于第二基极区域的掺杂浓度。