公开(公告)号：US11037802B2

公开(公告)日：2021-06-15

申请号：US16347207

申请日：2016-12-28

申请人： Intel Corporation

发明人： Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Sri Ranga Sai Boyapati ,  Sandeep Gaan ,  Srinivas V. Pietambaram

IPC分类号： H01L23/52 ,  H01L21/48 ,  H01L23/498 ,  H05K3/42 ,  H05K3/38

摘要： Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.

公开(公告)号：US10727184B2

公开(公告)日：2020-07-28

申请号：US16145683

申请日：2018-09-28

申请人： Intel Corporation

发明人： Siddharth K. Alur ,  Srinivas V. Pietambaram

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/498 ,  H01L25/065 ,  H01L21/02 ,  H01L23/00

摘要： Described are example microelectronic devices including structures, such as build-up layers, formed of a non-homogeneous photoimageable dielectric material. The non-homogeneous photoimageable dielectric material includes two regions forming opposite surfaces of the material. A first region includes a first carbon content, and a second region located above the first region includes a second carbon content which is greater than that of the first region. The second region of the photoimageable dielectric material provides enhanced adhesion with metal that may be deposited above the material, such as a sputtered metal seed layer to facilitate subsequent deposition of an electroless metal over the non-homogeneous photoimageable dielectric material.

公开(公告)号：US10714434B1

公开(公告)日：2020-07-14

申请号：US16236435

申请日：2018-12-29

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Aleksandar Aleksov

IPC分类号： H01L21/00 ,  H01L23/64 ,  H01L49/02 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

摘要： An embedded magnetic inductor coil is at least partially exposed in a recess that seats an embedded multi-chip interconnect bridge die on the coil. The embedded multi-chip interconnect bridge die provides a communications bridge between a dominant semiconductive device and a first semiconductive device.

公开(公告)号：US20190393178A1

公开(公告)日：2019-12-26

申请号：US16561974

申请日：2019-09-05

申请人： Intel Corporation

发明人： David Unruh ,  Srinivas V. Pietambaram

IPC分类号： H01L23/00

摘要： An electroless nickel, electroless palladium, electroless tin stack and. associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

公开(公告)号：US20190393145A1

公开(公告)日：2019-12-26

申请号：US16554008

申请日：2019-08-28

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48

摘要： A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20190333861A1

公开(公告)日：2019-10-31

申请号：US16474019

申请日：2017-03-29

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Rahul N. Manapalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

摘要： Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US20240194548A1

公开(公告)日：2024-06-13

申请号：US18065250

申请日：2022-12-13

申请人： Intel Corporation

发明人： Kristof Darmawikarta ,  Steve S. Cho ,  Hiroki Tanaka ,  Haobo Chen ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC分类号： H01L23/15 ,  C23C18/16 ,  C23C18/18 ,  C23C18/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/15 ,  C23C18/1639 ,  C23C18/165 ,  C23C18/1855 ,  C23C18/48 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1011 ,  H01L2924/1511 ,  H01L2924/15174 ,  H01L2924/15788

摘要： Apparatus and methods for electroless surface finishing on glass. A planarization process is performed on buildup dielectric and/or solder resist to create a flatter, more planar, upper surface for a substrate having a glass layer. Planarity is characterized by having surface variations of less than about 5 microns, as measured by recesses and/or protrusions. The planar surface enables finishing the substrate surface with an electroless NiPdAu process.

公开(公告)号：US20240188212A1

公开(公告)日：2024-06-06

申请号：US18061109

申请日：2022-12-02

申请人： Intel Corporation

发明人： Mohammad Mamunur Rahman ,  Brandon Christian Marin ,  Gang Duan ,  Srinivas V. Pietambaram ,  Suddhasattwa Nad ,  Rahul Manepalli

IPC分类号： H05K1/02 ,  H01L23/00 ,  H01L23/427 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46

CPC分类号： H05K1/0272 ,  H01L23/427 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H05K1/0201 ,  H05K1/112 ,  H05K3/4644 ,  H05K3/4697 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H05K2201/064

摘要： In one embodiment, an integrated circuit package substrate includes a core layer and a plurality of build-up layers on the core layer, each build-up layer comprising a dielectric and metal. The package substrate also includes a cavity, wherein a first portion of the cavity is defined in a first build-up layer, a second portion of the cavity is defined in a second build-up layer, and a third portion of the cavity connects the first portion with the second portion through at least one layer other than first build-up layer and the second build-up layer.

公开(公告)号：US20240186270A1

公开(公告)日：2024-06-06

申请号：US18074253

申请日：2022-12-02

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Claudio A. Alvarez Barros ,  Beomseok Choi ,  Gang Duan ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Hiroki Tanaka

IPC分类号： H01L23/64 ,  H01F10/32 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/645 ,  H01F10/3272 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0655

摘要： A microelectronic structure, a semiconductor package, an IC device assembly, and a method. The structure includes a core layer including an electrically non-conductive material; electrically conductive through core vias (TCVs) through the core layer; a dielectric layer on the core layer with electrically conductive structures extending therethrough and electrically coupled to the TCVs; and a magnetic inductor (MI) within at least one of the core layer or the build-up layer and including an antiferromagnetic (AF) structure. The AF structure includes a first ferromagnetic (FM) layer; an exchange coupling (EC) layer on the first FM layer and including a non-magnetic metal material; a second FM layer on the EC layer, the EC layer between the first FM layer and the second FM layer; and a pinning (P) layer including manganese and at least one of platinum or iridium, the second FM layer between the EC layer and the P layer.

公开(公告)号：US20240178207A1

公开(公告)日：2024-05-30

申请号：US18059089

申请日：2022-11-28

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC分类号： H01L25/16 ,  G02B6/42 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498

CPC分类号： H01L25/167 ,  G02B6/4259 ,  G02B6/426 ,  G02B6/428 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/08 ,  H01L2224/08121 ,  H01L2224/08225 ,  H01L2924/1903

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include an interposer having a surface, wherein a material of the interposer includes glass and the interposer includes through-glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bond interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical pathway through the interposer.