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公开(公告)号：US20150019831A1
公开(公告)日：2015-01-15
申请号：US14501107
申请日：2014-09-30
发明人： Gary A. Van Huben , Patrick J. Meaney , John S. Dodson , Scot H. Rider , James C. Gregerson , Eric E. Retter , Irving G. Baysah , Glenn D. Gilda , Lawrence D. Curley , Vesselina K. Papazova
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G06F13/1673 , G06F13/42 , G11C5/04 , G11C7/225 , G11C11/4076
摘要： A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.
摘要翻译： 用于存储器子系统中的双异步和同步存储器操作的计算机系统实现方法包括在存储器控制器和存储器缓冲器芯片之间建立同步通道。 模式选择器基于存储器缓冲器芯片的操作模式确定存储器缓冲器芯片的存储器域锁相环的参考时钟源。 基于同步的操作模式，将嵌套域锁相环的输出作为参考时钟源提供给存储器缓冲器芯片中的存储器域锁相环。 嵌套域锁相环可与存储器控制器的存储器控制器锁相环同步操作。 提供单独的参考时钟，独立于嵌套域锁相环作为基于异步操作模式的存储器域锁相环的参考时钟。
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公开(公告)号：US20140281326A1
公开(公告)日：2014-09-18
申请号：US13835521
申请日：2013-03-15
发明人： Gary A. Van Huben , Patrick J. Meaney , John S. Dodson , Scot H. Rider , James C. Gregerson , Eric E. Retter , Irving G. Baysah , Glenn D. Gilda , Lawrence D. Curley , Vesselina K. Papazova
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G06F13/1673 , G06F13/42 , G11C5/04 , G11C7/225 , G11C11/4076
摘要： Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.
摘要翻译： 实施例涉及双异步和同步存储器系统。 一个方面是一种系统，其包括存储器控制器和经由同步信道耦合到存储器控制器的存储器缓冲器芯片。 存储器缓冲器芯片包括被配置为与嵌套域中的存储器控制器同步通信的存储器缓冲器单元和被配置为与存储器域中的至少一个存储器接口端口通信的存储器缓冲适配器。 所述至少一个存储器接口端口可操作以访问至少一个存储器设备。 边界层连接到嵌套域和存储域，其中边界层可配置为在嵌套和存储器域之间以同步传输模式操作并且在嵌套和存储器域之间以异步传输模式操作。
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公开(公告)号：US20140281192A1
公开(公告)日：2014-09-18
申请号：US13835282
申请日：2013-03-15
IPC分类号： G11C7/10
CPC分类号： G06F13/16 , G06F3/0656 , G06F3/0659 , G06F13/1642 , G06F13/1689
摘要： Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.
摘要翻译： 实施例涉及MCU中的标签。 一个方面包括通过MCU的标签分配逻辑将命令标签分配给命令。 另一方面包括在与MCU通信的多个信道上发送命令和命令标签。 另一方面包括从多个频道中的每一个接收包括与命令标签对应的数据标签和完成标签之一的响应标签。 另一方面包括：基于从多个通道中的每一个接收数据标签，确定对应于该命令的读取数据是可用的。
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公开(公告)号：US20140281191A1
公开(公告)日：2014-09-18
申请号：US13835259
申请日：2013-03-15
IPC分类号： G11C7/10
CPC分类号： G06F12/06 , G06F12/0292 , G06F13/16 , G06F13/1694 , G06F13/4243 , G11C8/06
摘要： Embodiments relate to address mapping including generic bits. An aspect includes receiving an address including generic bits from a memory control unit (MCU) by a buffer module in a main memory. Another aspect includes mapping the generic bits to an address format corresponding to a type of dynamic random access memory (DRAM) in a memory subsystem associated with the buffer module by the buffer module. Yet another aspect includes accessing a physical location in the DRAM in the memory subsystem by the buffer module based on the mapped generic bits.
摘要翻译： 实施例涉及包括通用位的地址映射。 一个方面包括通过主存储器中的缓冲器模块从存储器控制单元（MCU）接收包括通用位的地址。 另一方面包括将通用位映射到与由缓冲器模块与缓冲器模块相关联的存储器子系统中的动态随机存取存储器（DRAM）类型对应的地址格式。 另一方面包括基于所映射的通用位，通过缓冲器模块访问存储器子系统中的DRAM中的物理位置。
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公开(公告)号：US20230060194A1
公开(公告)日：2023-03-02
申请号：US17446318
申请日：2021-08-30
发明人： Eric E. Retter , Lilith Hale , Brad William Michael , John Dodson
IPC分类号： G06F3/06
摘要： A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.
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公开(公告)号：US10713169B2
公开(公告)日：2020-07-14
申请号：US15873570
申请日：2018-01-17
IPC分类号： G06F12/0831 , G06F12/0817 , G06F12/0811
摘要： In response to receipt by a first coherency domain of a memory access request originating from a master in a second coherency domain and excluding from its scope a third coherency domain, coherence participants in the first coherency domain provide partial responses, and one of the coherence participants speculatively provides, to the master, data from a target memory block. The data includes a memory domain indicator indicating whether the memory block is cached, if at all, only within the first coherency domain. Based on the partial responses a combined response is generated representing a systemwide coherence response to the memory access request. In response to the combined response indicating success and the memory domain indicator indicating that a valid copy of the memory block may be cached outside the first coherence domain, the master discards the speculatively provided data and reissues the memory access request with a larger broadcast scope.
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公开(公告)号：US10387310B2
公开(公告)日：2019-08-20
申请号：US15873515
申请日：2018-01-17
IPC分类号： G06F12/00 , G06F12/0817 , G06F12/0831 , G06F12/0811
摘要： A data processing system includes first and second coherency domains and employs a snoop-based coherence protocol. In response to receipt by the first coherency domain of a memory access request originating from a master in the second coherency domain, a plurality of coherence participants in the first coherency domain provides partial responses for the memory access request to an early combined response generator. Based on the partial responses, the early combined response generator generates and transmits, to a memory controller of a system memory in the first coherency domain, an early combined response of only the first coherency domain. Based on the early combined response, the memory controller transmits, to the master prior to receipt by the memory controller of a systemwide combined response for the memory access request, data associated with a target memory address and/or coherence permission for the target memory address.
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公开(公告)号：US20190250682A1
公开(公告)日：2019-08-15
申请号：US16397822
申请日：2019-04-29
发明人： Irving G. Baysah , John S. Dodson , Karthick Rajamani , Eric E. Retter , Scot H. Rider , Todd Jon Rosedahl , Gregory Scott Still , Gary Van Huben , Malcolm S. Allen-Ware
IPC分类号： G06F1/26 , G06F11/34 , G06F1/32 , G06F1/3206 , G06F1/3203 , G06F11/30 , G06F1/20
CPC分类号： G06F1/26 , G06F1/206 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F11/3037 , G06F11/3409 , Y02D10/11 , Y02D10/16
摘要： A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.
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公开(公告)号：US09594647B2
公开(公告)日：2017-03-14
申请号：US15262111
申请日：2016-09-12
发明人： Patrick J. Meaney , Glenn D. Gilda , Eric E. Retter , John S. Dodson , Gary A. Van Huben , Brad W. Michael , Stephen J. Powell
IPC分类号： G06F11/16 , G06F1/12 , G11C11/4076 , G11C11/4093 , G06F1/10 , G06F1/04
CPC分类号： G06F11/1679 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/32 , G06F11/1497 , G06F11/1604 , G06F11/1675 , G06F13/1689 , G06F13/1694 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C29/52
摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.
摘要翻译： 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。
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公开(公告)号：US09495254B2
公开(公告)日：2016-11-15
申请号：US15073699
申请日：2016-03-18
发明人： Patrick J. Meaney , Glenn D. Gilda , Eric E. Retter , John S. Dodson , Gary A. Van Huben , Brad W. Michael , Stephen J. Powell
CPC分类号： G06F11/1679 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/32 , G06F11/1497 , G06F11/1604 , G06F11/1675 , G06F13/1689 , G06F13/1694 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C29/52
摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.
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