公开(公告)号：US4103184A

公开(公告)日：1978-07-25

申请号：US722102

申请日：1976-09-10

申请人： Yasoji Suzuki ,  Tadashi Kuroda

发明人： Yasoji Suzuki ,  Tadashi Kuroda

IPC分类号： G04G3/02 ,  H03K21/00 ,  H03K23/40 ,  H03K23/52 ,  H03K23/54 ,  H03K23/08

CPC分类号： H03K23/54 ,  H03K23/40

摘要： A frequency divider wherein an output from a crystal oscillating circuit comprising a crystal oscillating element and an inverter connected in parallel therewith is sent forth as a one-phase oscillation pulse for frequency division from the input or output side of the inverter to the .phi. input terminal of a counter formed of a plurality of insulated gate field effect transistors (hereinafter abbreviated "IGFET's"). The counter comprises a plurality of cascade-connected complementary unit circuits each consisting of a series circuit of IGFET's connected between power supply terminals with IGFET's disposed on one side of an imaginary border line connecting the input and output terminals of said complementary unit circuit chosen to have a different channel type from those provided on the other side of said border line, and wherein at least the first and last complementary unit circuits' IGFET's are provided in different numbers on both sides of said border line. A one-phase pulse from the crystal oscillating circuit is supplied to the gate electrodes of the prescribed different IGFET's constituting the plural complementary unit circuits, and an output from the last complementary unit circuit of the counter is conducted to the gate electrodes of the prescribed different IGFET's constituting the other complementary unit circuits.

公开(公告)号：US4088958A

公开(公告)日：1978-05-09

申请号：US722761

申请日：1976-09-13

申请人： Yasoji Suzuki ,  Tomohisa Shigematsu ,  Nawoyuki Kokado ,  Yukinori Kudo

发明人： Yasoji Suzuki ,  Tomohisa Shigematsu ,  Nawoyuki Kokado ,  Yukinori Kudo

IPC分类号： G04G15/00 ,  G05B19/02 ,  G05B19/045 ,  G09G5/00 ,  G09G5/22 ,  H03J5/02 ,  H04B1/06 ,  H04N5/44 ,  H04B1/16

CPC分类号： H03J5/0245 ,  G04G15/006 ,  G05B19/045 ,  H04N5/45

摘要： An integrated circuit for a programmable television receiver comprises a memory for storing a plurality of programs, a digital clock and a character generating circuit for generating character signals for displaying the programs in the memory and/or time of the digital clock on the screen of a television receiver. The integrated circuit uses dynamic circuits to reduce the number of elements required, and CMOS transistors to attain a lower power dissipation.

摘要翻译： 一种用于可编程电视接收机的集成电路包括用于存储多个节目的存储器，数字时钟和字符产生电路，用于产生用于在存储器中显示节目的字符信号和/或数字时钟的时间在 电视接收机。 该集成电路使用动态电路来减少所需的元件数量，并使用CMOS晶体管来实现更低的功耗。

公开(公告)号：US4020362A

公开(公告)日：1977-04-26

申请号：US592643

申请日：1975-07-02

申请人： Yasoji Suzuki ,  Kenshi Manabe ,  Masataka Hirasawa

发明人： Yasoji Suzuki ,  Kenshi Manabe ,  Masataka Hirasawa

IPC分类号： H03K23/64 ,  G11C19/18 ,  H03K23/42 ,  H03K23/44 ,  H03K23/54 ,  H03K21/36 ,  H03K23/08

CPC分类号： G11C19/184 ,  H03K23/42 ,  H03K23/44

摘要： A counter comprises a cascade connection of an inverter stage and n one-bit shift register stages, the latter being operative in response to clock signals to be counted and each having a data-readin or front half-bit shift register stage and a data-readout or rear half-bit shift register stage. The output of the final stage in the cascade connection is coupled to the input of the first stage in the cascade connection. The output of the final stage is also coupled to an additional input of consecutive 1st to X-th shift register stages or consecutive 2nd to (X-1)-th shift register stages of an X-th shift register stage to constitute a scale-of-2n-X or 2n-(X-1) counter.

摘要翻译： 计数器包括逆变器级和n个1位移位寄存器级的级联连接，后者可响应于待计数的时钟信号而工作，每个具有数据读或前半位移位寄存器级和数据 - 读出或后半位移位寄存器级。 级联连接中的最后级的输出在级联连接中耦合到第一级的输入端。 最后级的输出还耦合到第X移位寄存器级的连续的第1至第X移位寄存器级或连续的第2至第（X-1）移位寄存器级的附加输入， 的2n-X或2n-（X-1）计数器。

公开(公告)号：US4912749A

公开(公告)日：1990-03-27

申请号：US149606

申请日：1988-01-28

申请人： Tadashi Maruyama ,  Yukio Wada ,  Tomohisa Shigematsu ,  Yasoji Suzuki ,  Makoto Yoshizawa

发明人： Tadashi Maruyama ,  Yukio Wada ,  Tomohisa Shigematsu ,  Yasoji Suzuki ,  Makoto Yoshizawa

IPC分类号： G11C17/00 ,  B42D15/02 ,  B42D15/10 ,  G03H1/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0433 ,  G11C16/10

摘要： In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.

公开(公告)号：US4414515A

公开(公告)日：1983-11-08

申请号：US205629

申请日：1980-11-10

申请人： Yasoji Suzuki ,  Kenji Matsuo

发明人： Yasoji Suzuki ,  Kenji Matsuo

IPC分类号： H03K3/023 ,  H03K3/03 ,  H03K3/354 ,  H03K4/50

CPC分类号： H03K3/354 ,  H03K3/023 ,  Y10S331/03

摘要： A CR oscillation circuit is provided which includes inverters which are connected in series and whose operating current paths between a power source terminal and a ground terminal are connected in series with a constant current source. In certain embodiments, a resistor is connected between the output terminal of one inverter and the input terminal of the first inverter, and a capacitor is connected between the output terminal of another inverter and the input terminal of the first inverter. The CR oscillation circuit further has a constant current source connected in series with the operating current path of said inverters between the power source terminal and the ground terminal. In other embodiments, the resistor and capacitor are connected in parallel and to the input of an inverter.

摘要翻译： 提供一种CR振荡电路，其包括串联连接的反相器，其电源端子和接地端子之间的工作电流路径与恒定电流源串联连接。 在某些实施例中，电阻器连接在一个逆变器的输出端和第一反相器的输入端之间，电容器连接在另一个反相器的输出端和第一个反相器的输入端之间。 CR振荡电路还具有与电源端子和接地端子之间的所述反相器的工作电流路径串联连接的恒流源。 在其他实施例中，电阻器和电容器并联连接到逆变器的输入端。

公开(公告)号：US4404663A

公开(公告)日：1983-09-13

申请号：US234438

申请日：1981-02-13

申请人： Yukihiro Saeki ,  Fuminari Tanaka ,  Yasoji Suzuki

发明人： Yukihiro Saeki ,  Fuminari Tanaka ,  Yasoji Suzuki

IPC分类号： G06F1/18 ,  G06F3/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C5/063 ,  G11C7/10 ,  G11C7/1006

摘要： An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.

摘要翻译： 一种集成电路，其中门电路设置在安装在半导体衬底上的总线上。 门电路用于将未使用的电路块与通过用于高速数据传输的输入 - 输出电路连接到总线的其它电路块分离，从而减少可能通过分离的总线赋予总线的寄生电容 电路块。 输入输出电路由时钟反相器构成。 门电路由CxMOS传输门形成。 输入输出电路和门电路如此连接，使逆变器的门打开，则CxMOS传输门关闭; 并且逆变器的门关闭​​，则CxMOS传输门打开。

公开(公告)号：US4291274A

公开(公告)日：1981-09-22

申请号：US096056

申请日：1979-11-20

申请人： Yasoji Suzuki ,  Nobuyuki Kamimaru

发明人： Yasoji Suzuki ,  Nobuyuki Kamimaru

IPC分类号： G01R25/00 ,  H02N2/06 ,  H03D13/00 ,  H03K5/26

CPC分类号： H03D13/004 ,  G01R25/005

摘要： A phase detector circuit having four dominant type flip-flop circuits and at least one logic gate. The phase detector circuit is responsive to changes of two input signals, and produces output signals related to the relative phase of the input signals having duty cycle. The output signals have a predetermined level only for the period the phases of the input signals differ. When the phases of the input signals are the same, the output signals of the phase detector circuit will be at another level.

摘要翻译： 一种具有四个显性触发器电路和至少一个逻辑门的相位检测器电路。 相位检测器电路响应两个输入信号的变化，并且产生与具有占空比的输入信号的相对相关的输出信号。 输出信号仅在输入信号的相位不同的周期内具有预定电平。 当输入信号的相位相同时，相位检测器电路的输出信号将处于另一级。

公开(公告)号：US4230951A

公开(公告)日：1980-10-28

申请号：US882147

申请日：1978-02-28

申请人： Yasoji Suzuki ,  Susumu Kouyama

发明人： Yasoji Suzuki ,  Susumu Kouyama

IPC分类号： G11C27/04 ,  G11C19/28 ,  H03H11/26 ,  H03K5/15

CPC分类号： H03K5/15013 ,  G11C19/282

摘要： A plurality of signal lines receiving signals with different phases are connected to the reference potential point through switching elements. The switching elements connected to signal lines other than the signal line receiving an active signal are rendered conductive by the active signal on the signal line and the other signal lines are led to the reference potential.

摘要翻译： 接收不同相位的信号的多条信号线通过开关元件连接到参考电位点。 连接到接收有源信号的信号线以外的信号线的开关元件由信号线上的有源信号导通，其他信号线被引导到参考电位。

公开(公告)号：US4217535A

公开(公告)日：1980-08-12

申请号：US864085

申请日：1977-12-23

申请人： Yasoji Suzuki ,  Takeshi Hitotsuyanagi ,  Tetsuya Iida

发明人： Yasoji Suzuki ,  Takeshi Hitotsuyanagi ,  Tetsuya Iida

IPC分类号： G01R31/36 ,  G05F3/24 ,  H02J7/10 ,  H03K3/26

CPC分类号： G01R19/16542 ,  G05F3/245 ,  G05F3/247

摘要： A constant-voltage circuit in which a diode and an MOS transistor are connected in series between power supply terminals between which a battery power source is connected. The MOS transistor is biased to operate in the saturation region. The forward voltage drop across the diode is kept substantially constant independent of variations in battery voltage and temperature. This constant-voltage circuit may preferably be used in a battery checker circuit for detecting the end of battery life.

摘要翻译： 一种恒压电路，其中二极管和MOS晶体管串联连接在其上连接有电池电源的电源端子之间。 MOS晶体管被偏置以在饱和区域中工作。 独立于电池电压和温度的变化，二极管两端的正向压降保持基本恒定。 这种恒压电路可以优选地用于检测电池寿命结束的电池检查电路中。

公开(公告)号：US4217502A

公开(公告)日：1980-08-12

申请号：US941256

申请日：1978-09-11

申请人： Yasoji Suzuki ,  Ryuzo Shiraki

发明人： Yasoji Suzuki ,  Ryuzo Shiraki

IPC分类号： H03K19/0185 ,  H03K19/094 ,  H03K19/20 ,  H03K17/04 ,  H03K19/08

CPC分类号： H03K19/09429 ,  H03K19/018521

摘要： An output circuit is provided in which a first IG-FET of a first conductivity type is connected between a first potential supply terminal and an output terminal and having its substrate controlled by a third potential higher than the first potential of the first potential supply terminal and a second IG-FET of a second conductivity type connected between a second potential supply terminal having a second potential lower than the first potential and the output terminal and having its substrate electrode supplied with the second potential. A control circuit is further provided which receives an input signal and control signal and controls the output circuit to permit the latter to produce one of the first potential, second potential and high impedance state. The output circuit and control circuit are combined to provide a converter circuit for converting the level of a CML (complementary MOS Transistor Logic) to a TTL (Transistor-Transistor Logic). A compensation circuit is further provided which, when a potential on the output terminal is shifted from the second potential to the first potential, permits a rise of the second potential to be sharpened. The compensation circuit includes a third IG-FET of a second conductivity type connected between the first potential supply terminal and the output terminal.

摘要翻译： 提供了一种输出电路，其中第一导电类型的第一IG-FET连接在第一电位供给端子和输出端子之间，并且其基板受到比第一电位供应端子的第一电位高的第三电位的控制， 第二导电类型的第二IG-FET连接在具有低于第一电位的第二电位的第二电位供应端和输出端之间，并且其基板电极被提供有第二电位。 还提供控制电路，其接收输入信号和控制信号，并控制输出电路以允许输出信号产生第一电位，第二电位和高阻抗状态之一。 输出电路和控制电路被组合以提供用于将CML（互补MOS晶体管逻辑）的电平转换为TTL（晶体管 - 晶体管逻辑）的转换器电路。 还提供补偿电路，当输出端子上的电位从第二电位移动到第一电位时，允许第二电位的上升被削尖。 补偿电路包括连接在第一电位供给端子和输出端子之间的第二导电类型的第三IG-FET。