公开(公告)号：US5875086A

公开(公告)日：1999-02-23

申请号：US718227

申请日：1996-09-20

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H02H9/04

CPC分类号： H02H9/046 ,  H01L27/0251

摘要： A protective system incorporated in a semiconductor integrated circuit device has a shared discharging line and a plurality of protective circuits each having a diode and a lateral bipolar transistor coupled between an associated pad and the shared discharging line. Surge voltage applied to the pad is discharged through the associated protective circuit to the shared discharging line so that a main circuit is not destroyed by the surge voltage.

摘要翻译： 结合在半导体集成电路器件中的保护系统具有共享放电线和多个保护电路，每个保护电路具有耦合在相关联的焊盘和共享放电线之间的二极管和横向双极晶体管。 施加到焊盘的浪涌电压通过相关联的保护电路放电到共享放电线，使得主电路不被浪涌电压破坏。

公开(公告)号：US5859451A

公开(公告)日：1999-01-12

申请号：US717601

申请日：1991-06-19

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10808 ,  H01L27/10829

摘要： A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.

摘要翻译： 一种存储单元，包括形成在半导体衬底的主表面上的MOSFET和存储电极的信息存储电容器，所述存储电容器形成在所述衬底中或衬底上，以便与所述MOSFET的漏极区域接触;以及电容器电极， 具有电容器绝缘体膜的存储电极夹在存储电极和电容器电极之间。 存储电极通过形成在漏极区域和存储电极区域之间的薄的阻挡层与MOSFET的漏极区域连接，以防止存储电极中的杂质扩散到漏极区域。

公开(公告)号：US5706156A

公开(公告)日：1998-01-06

申请号：US591025

申请日：1996-01-25

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  H01L23/00 ,  H01L27/02 ,  H01L27/04 ,  H03K19/003 ,  H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0251 ,  H01L27/0255

摘要： A semiconductor device has a protective circuitry including a common discharge line, a first protective device connected between one of input/output terminals and the discharge line, and a second protective device connected between one of Vcc and ground terminals and the discharge line. The second protective device has an on-resistance as much as 1/2 of the on-resistance of the first protective device. Each of the power terminals and ground terminals generally has a large capacitance to accumulate a large amount of electric charge during a CDM test after charging of the semiconductor device as a whole. The low on-resistance prevents the inner circuit and input/output buffers of the semiconductor device from being applied with a higher potential during subsequent grounding of the semiconductor device in the CDM test.

摘要翻译： 半导体器件具有保护电路，其包括公共放电线，连接在输入/输出端子之一和放电线之间的第一保护器件，以及连接在Vcc和接地端子之一与放电线之间的第二保护器件。 第二保护装置的导通电阻与第一保护装置的导通电阻的+ E，fra 1/2 + EE一样多。 每个电源端子和接地端子通常具有大的电容，以在半导体器件整体充电之后的CDM测试期间积累大量的电荷。 低导通电阻防止半导体器件的内部电路和输入/输出缓冲器在CDM测试中的半导体器件的后续接地期间被施加更高的电位。

公开(公告)号：US5689120A

公开(公告)日：1997-11-18

申请号：US730273

申请日：1996-10-15

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L27/1203 ,  H01L27/10808 ,  H01L29/41775

摘要： The present invention provides a field effect transistor comprising the following elements. An insulation film is provided on a semiconductor substrate. The insulation film has an opening positioned on a predetermined region of the semiconductor substrate. A first polysilicon film is provided over the insulation film. A second polysilicon film is provided in contact with the first polysilicon film. The second polysilicon film extends on inside walls of the opening of the insulation film and over a peripheral portion of the predetermined region of the semiconductor substrate so that the first polysilicon film is connected through the second polysilicon film to the peripheral portion in the predetermined region of the semiconductor substrate. A gate insulation film is selectively provided, which extends on the predetermined region, except on the peripheral portion, of the semiconductor substrate and further extends on the second polysilicon film and a part of the first polysilicon film around the second polysilicon film. A gate electrode is provided on the gate insulation film to define a composite channel region raider the gate insulation film so that the composite channel region extends through the first and second polysilicon films under the gate insulation film as well as through the semiconductor substrate under the gate insulation film. Source and drain regions are selectively provided in the first polysilicon film except under the gate insulation film so that the source and drain regions are connected through the composite channel region.

摘要翻译： 本发明提供一种包括以下元件的场效应晶体管。 绝缘膜设置在半导体衬底上。 绝缘膜具有位于半导体基板的预定区域上的开口。 第一多晶硅膜设置在绝缘膜上。 提供与第一多晶硅膜接触的第二多晶硅膜。 第二多晶硅膜延伸在绝缘膜的开口的内壁上并在半导体衬底的预定区域的周边部分上延伸，使得第一多晶硅膜通过第二多晶硅膜连接到第二多晶硅膜的预定区域的周边部分 半导体衬底。 选择性地设置栅极绝缘膜，该栅极绝缘膜在半导体衬底的外周部分的预定区域上延伸，并且还在第二多晶硅膜上延伸并且在第二多晶硅膜周围延伸第一多晶硅膜的一部分。 栅极电极设置在栅极绝缘膜上以限定栅极绝缘膜的复合沟道区域，使得复合沟道区域延伸穿过栅极绝缘膜下方的第一和第二多晶硅膜以及通过栅极下方的半导体衬底 绝缘膜。 源极和漏极区域选择性地设置在除了栅极绝缘膜之下的第一多晶硅膜中，使得源极和漏极区域通过复合沟道区域连接。

公开(公告)号：US20130002394A1

公开(公告)日：2013-01-03

申请号：US13635181

申请日：2011-05-11

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01C1/16 ,  H01C17/00 ,  B82Y15/00

CPC分类号： H01C7/02 ,  G01J5/20 ,  G01J2005/0077 ,  Y10T29/49082

摘要： A polymer film 102 is formed on a substrate 101, a thermistor resistor 106 is formed on the polymer film 102, and a light reflecting film 104 is formed between the thermistor resistor 106 and the substrate 101. For this reason, if infrared rays or terahertz waves are incident from above, a part is absorbed by the thermistor resistor 106, and most transmits the polymer film 102 and is reflected by the light reflecting film 104. When the distance between the thermistor resistor 106 and the light reflecting film 104 is d, a light component having a wavelength expressed by d=l/4 and equal to or smaller than l resonates and changes to heat, and the temperature of the thermistor resistor 106 rises. A change in resistance with a rise in the temperature of the thermistor resistor 106 is detected, thereby detecting the intensity of an infrared ray or a terahertz wave.

摘要翻译： 聚合物膜102形成在基板101上，在聚合物膜102上形成热敏电阻电阻器106，并且在热敏电阻电阻器106和基板101之间形成光反射膜104.因此，如果红外线或太赫兹 波从上方入射，部分被热敏电阻电阻106吸收，大部分透射聚合物膜102并被光反射膜104反射。当热敏电阻电阻106和光反射膜104之间的距离为d时， 具有由d = 1/4并且等于或小于1的波长表示的波长的光分量谐振并变热，并且热敏电阻电阻器106的温度升高。 检测到热敏电阻电阻器106的温度升高时的电阻变化，从而检测红外线或太赫兹波的强度。

公开(公告)号：US08085112B2

公开(公告)日：2011-12-27

申请号：US13187910

申请日：2011-07-21

申请人： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

发明人： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

IPC分类号： H03H7/38

CPC分类号： H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

摘要： According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; the length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

摘要翻译： 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者根据通过三维全波模拟获得的数字图，定义为在时域中提供极小的超额感抗 。

公开(公告)号：US08035992B2

公开(公告)日：2011-10-11

申请号：US12089483

申请日：2006-10-10

申请人： Taras Kushta ,  Kaoru Narita

发明人： Taras Kushta ,  Kaoru Narita

IPC分类号： H05K9/00

CPC分类号： H05K1/0222 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/115 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718

摘要： Provided are vertical transitions which have the high electrical performance and the high shielding properties in the wide frequency band in a multilayer PCB, printed circuit boards with the vertical transitions and semiconductor packages with the printed circuit boards and semiconductor chips. In vertical transitions for a multilayer PCB, a wave guiding channel is a conductor which includes at least more than one of signal vias 201, an assembly of ground vias 202 surrounding the signal via, ground plates from conductor layers of the PCB connected to the ground vias, closed ground striplines 205 connecting the ground vias and power supply layer.

摘要翻译： 提供了在多层PCB中的宽频带中具有高电性能和高屏蔽性能的垂直转换，具有垂直转换的印刷电路板和具有印刷电路板和半导体芯片的半导体封装。 在多层PCB的垂直转换中，波导通道是包括至少多于一个信号通孔201的导体，围绕信号通孔的接地通孔202的组件，与连接到地面的PCB的导体层的接地板 通孔，连接接地通孔和电源层的闭合接地带状线205。

公开(公告)号：US07952365B2

公开(公告)日：2011-05-31

申请号：US11817280

申请日：2006-03-22

申请人： Kaoru Narita ,  Taras Kushta

发明人： Kaoru Narita ,  Taras Kushta

IPC分类号： G01R27/04 ,  G01R27/28 ,  G01J3/00

CPC分类号： H05K1/0268 ,  G01R27/2617 ,  G01R31/2805 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09618 ,  H05K2201/10068

摘要： A plurality of through-hole vias connected to conductor layers is disposed with gaps left between these vias around opening parts disposed in the conductor layers in a printed board in which these conductor layers are disposed parallel to each other so as to sandwich a dielectric layer in between. Furthermore, through-hole vias used for excitation are disposed in the opening parts of the conductor layers and regions of the dielectric layer matching these opening parts in a non-contact manner with the conductor layers. When the complex dielectric constant is measured, a high-frequency power is applied to the through-hole vias, and the power loss between the through-hole vias and the conductor layers is measured by the S parameter method. As a result, the complex dielectric constant and the frequency dependency of this complex dielectric constant can be measured with a high precision in a frequency range extending from several gigahertzes to 20 GHz, and there is no electrical interference with other parts even when this resonator is mounted on a board.

摘要翻译： 连接到导体层的多个通孔过孔被布置成在印刷电路板的布置在导体层中的开口部分周围的这些通孔之间留有间隙，其中这些导体层彼此平行设置，以将电介质层夹在 之间。 此外，用于激励的通孔过孔以与导体层非接触的方式设置在导体层的开口部分和与这些开口部分匹配的电介质层的区域。 当测量复介电常数时，对通孔通孔施加高频功率，通过S参数法测量通孔和导体层之间的功率损耗。 结果，可以在从几千兆赫到20GHz的频率范围内以高精度测量该复合介电常数的复介电常数和频率依赖性，即使该谐振器是 安装在板上。

公开(公告)号：US20090091406A1

公开(公告)日：2009-04-09

申请号：US12249273

申请日：2008-10-10

申请人： Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

发明人： Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC分类号： H01P1/00

CPC分类号： H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

摘要翻译： 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US20070205847A1

公开(公告)日：2007-09-06

申请号：US10598134

申请日：2005-03-09

申请人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

发明人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

IPC分类号： H01P5/02

CPC分类号： H05K1/0222 ,  H05K1/0269 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predetermined clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.

摘要翻译： 一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件， 多层PCB的导体层的接地板组以及间隙孔。 在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部 通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置 根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。