公开(公告)号：US20060024875A1

公开(公告)日：2006-02-02

申请号：US11234118

申请日：2005-09-26

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US20050118762A1

公开(公告)日：2005-06-02

申请号：US10998804

申请日：2004-11-30

申请人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

发明人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

IPC分类号： C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/65 ,  H01L21/32136 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/91

摘要： After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

摘要翻译： 在形成上部电极保护膜使得其与上部电极的钌膜牢固接触而不损坏钌膜之后，蚀刻上部电极，由此获得漏电流不增加的MIM电容器 以使上电极的钌膜氧化。

公开(公告)号：US06894334B2

公开(公告)日：2005-05-17

申请号：US10376329

申请日：2003-03-03

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US06781172B2

公开(公告)日：2004-08-24

申请号：US09800493

申请日：2001-03-08

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

IPC分类号： H01L2976

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L28/55

摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

摘要翻译： 一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素 选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

公开(公告)号：US06737318B2

公开(公告)日：2004-05-18

申请号：US09998654

申请日：2001-12-03

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.

摘要翻译： 公开了一种制造半导体集成电路器件的方法，该半导体集成电路器件具有形成在诸如DRAM之类的半导体衬底上的开关MISFET和电容元件。 电容器元件的电介质膜形成为与其上的电容器电极层共同扩展。 电容器元件的上电极形成为比下电极大。

公开(公告)号：US06639263B2

公开(公告)日：2003-10-28

申请号：US10255714

申请日：2002-09-27

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L27108

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

摘要翻译： 本发明的目的是提供一种具有存储电容器和使用铜作为主导电膜的布线的高可靠性半导体器件。 根据上述目的，本发明提供一种半导体器件，包括：半导体衬底; 形成在所述半导体基板的所述主面侧的作为第一电极的保持电容器和布置成放置电容器绝缘膜的第二电极; 形成在所述半导体衬底的主表面侧并且包括所述铜（Cu）元件的布线导体; 以及形成在所述布线导体的表面上的第一膜; 其中构成第一膜的材料和构成第一电极和/或第二电极的材料包括相同的元件。

公开(公告)号：US06638811B2

公开(公告)日：2003-10-28

申请号：US10157977

申请日：2002-05-31

申请人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

发明人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

IPC分类号： H01L218242

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/40

摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

摘要翻译： 在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方 从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

公开(公告)号：US06548847B2

公开(公告)日：2003-04-15

申请号：US09899921

申请日：2001-07-09

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US06528403B2

公开(公告)日：2003-03-04

申请号：US10013454

申请日：2001-12-13

申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

IPC分类号： H01L214763

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

公开(公告)号：US06417045B1

公开(公告)日：2002-07-09

申请号：US09642586

申请日：2000-08-22

申请人： Isamu Asano ,  Robert Tsu

发明人： Isamu Asano ,  Robert Tsu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。