公开(公告)号：US20180012785A1

公开(公告)日：2018-01-11

申请号：US15634365

申请日：2017-06-27

Applicant: Lam Research Corporation

Inventor： Alexander Matyushkin ,  John Patrick Holland ,  Harmeet Singh ,  Alexi Marakhtanov ,  Keith Gaff ,  Zhigang Chen ,  Fleix Kozakevich

IPC: H01L21/683 ,  H01L21/67

CPC classification number: H01L21/6833 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6831

Abstract: A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond layer. The ceramic layer includes a first region and a second region located radially outward of the first region, the first region has a first thickness, the second region has a second thickness, and the first thickness is greater than the second thickness.

公开(公告)号：US20170229327A1

公开(公告)日：2017-08-10

申请号：US15497992

申请日：2017-04-26

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Keith Gaff ,  Neil Benjamin ,  Keith Comendant

IPC: H01L21/67 ,  H01J37/32 ,  C23C4/10 ,  C23C4/134 ,  C23C14/50 ,  C23C16/509 ,  C23C14/34 ,  C23C14/10 ,  C23C16/40 ,  C23C16/458 ,  C23C16/46 ,  H01L21/683 ,  C23C14/54

CPC classification number: H01L21/67103 ,  C23C4/10 ,  C23C4/134 ,  C23C14/10 ,  C23C14/34 ,  C23C14/50 ,  C23C14/541 ,  C23C16/401 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/509 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32449 ,  H01J37/32724 ,  H01J2237/327 ,  H01J2237/332 ,  H01J2237/3321 ,  H01J2237/3323 ,  H01J2237/334 ,  H01J2237/3342 ,  H01J2237/3343 ,  H01L21/02274 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H01L21/6833 ,  H05B1/0233 ,  H05B3/00 ,  H05B3/26 ,  Y10T29/49083 ,  Y10T29/49099

Abstract: A substrate support is provided, is configured to support a substrate in a plasma processing chamber, and includes first, second and third insulative layers, conduits and leads. The first insulative layer includes heater zones arranged in rows and columns. The second insulative layer includes conductive vias. First ends of the conductive vias are connected respectively to the heater zones. Second ends of the conductive vias are connected respectively to power supply lines. The third insulative layer includes power return lines. The conduits extend through the second insulative layer and into the third insulative layer. The leads extend through the conduits and connect to the heater zones. The heater zones are connected to the power return lines by the leads and are configured to heat corresponding portions of the substrate to provide a predetermined temperature profile across the substrate during processing of the substrate in the plasma processing chamber.

公开(公告)号：US09646861B2

公开(公告)日：2017-05-09

申请号：US14056604

申请日：2013-10-17

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Keith Gaff ,  Neil Benjamin ,  Keith Comendant

IPC: H05B1/02 ,  H01L21/67 ,  C23C14/54 ,  C23C16/458 ,  H01L21/683 ,  H01L21/3065 ,  H05B3/26 ,  H05B3/00 ,  C23C14/50 ,  C23C16/46 ,  C23C16/509 ,  H01J37/32 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/67103 ,  C23C14/50 ,  C23C14/541 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/509 ,  H01J37/32091 ,  H01J37/32724 ,  H01J2237/327 ,  H01J2237/332 ,  H01J2237/3321 ,  H01J2237/3323 ,  H01J2237/334 ,  H01J2237/3342 ,  H01J2237/3343 ,  H01L21/02274 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H05B1/0233 ,  H05B3/00 ,  H05B3/26 ,  Y10T29/49083 ,  Y10T29/49099

Abstract: A heating plate for use in a substrate support is configured to provide temperature profile control of a substrate supported on the substrate support in a vacuum chamber of a substrate processing apparatus. The heating plate includes an independently controllable heater zones operable to tune a temperature profile on an upper surface of the heating plate. The heater zones are each powered by two or more power lines wherein each power line is electrically connected to a different group of the heater zones and each respective heater zone is electrically connected to a different pair of power lines.

公开(公告)号：US20160300741A1

公开(公告)日：2016-10-13

申请号：US15183260

申请日：2016-06-15

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Keith Gaff ,  Neil Benjamin ,  Keith Comendant

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/683

CPC classification number: H01L21/67103 ,  C23C4/10 ,  C23C4/134 ,  C23C14/10 ,  C23C14/34 ,  C23C14/50 ,  C23C14/541 ,  C23C16/401 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/509 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32449 ,  H01J37/32724 ,  H01J2237/327 ,  H01J2237/332 ,  H01J2237/3321 ,  H01J2237/3323 ,  H01J2237/334 ,  H01J2237/3342 ,  H01J2237/3343 ,  H01L21/02274 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H01L21/6833 ,  H05B1/0233 ,  H05B3/00 ,  H05B3/26 ,  Y10T29/49083 ,  Y10T29/49099

Abstract: A substrate support in a semiconductor plasma processing apparatus, comprises multiple independently controllable thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the thermal zones. A substrate support in which the substrate support is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the substrate support include bonding together ceramic or polymer sheets having thermal zones, power supply lines, power return lines and vias.

Abstract translation: 半导体等离子体处理装置中的衬底支撑件包括以可伸缩多路复用布局布置的多个可独立控制的热区，以及用于独立地控制和加热热区的电子装置。 其中结合衬底支撑件的衬底支撑件包括静电夹持电极和温度控制的底板。 用于制造衬底支撑体的方法包括将具有热区，电源线，功率返回线和通孔的陶瓷或聚合物片粘合在一起。

公开(公告)号：US20150181683A1

公开(公告)日：2015-06-25

申请号：US14136826

申请日：2013-12-20

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Christopher Kimball ,  Keith Gaff ,  Tyler Gloski

IPC: H05F3/02 ,  H01L21/683

CPC classification number: H01L21/6833

Abstract: A semiconductor wafer processing apparatus for processing semiconductor wafers comprises a semiconductor wafer processing chamber in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber, and an electrostatic chuck assembly. The electrostatic chuck assembly comprises a support surface in a layer of ceramic material on which the semiconductor wafer is supported during processing of the wafer in the chamber, at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to the wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode, and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode.

Abstract translation: 一种用于处理半导体晶片的半导体晶片处理装置，包括处理半导体晶片的半导体晶片处理室，与处理室流体连通的处理气体源，其适于将处理气体供应到处理室中，适于排出的真空源 来自处理室的处理气体和副产物以及静电吸盘组件。 静电卡盘组件包括在陶瓷材料层中的支撑表面，其中半导体晶片在腔室中的晶片处理期间被支撑，至少一个静电夹持电极嵌入在陶瓷材料层中，该至少一个静电夹持 电极，其可操作以当静电钳位电压施加到所述夹持电极时将静电夹持力施加到所述支撑表面上的所述晶片;以及至少一个在所述至少一个静电夹持电极上方的陶瓷材料层中的所述电极， 当静电钳位电压不再施加到夹紧电极时，提供用于在晶片和支撑表面之间排出任何残留电荷的路径。

公开(公告)号：US09012243B2

公开(公告)日：2015-04-21

申请号：US14470544

申请日：2014-08-27

Applicant: Lam Research Corporation

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/66 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US08852964B2

公开(公告)日：2014-10-07

申请号：US13758266

申请日：2013-02-04

Applicant: Lam Research Corporation

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。