公开(公告)号：US20100141322A1

公开(公告)日：2010-06-10

申请号：US12328042

申请日：2008-12-04

申请人： Lew G. Chua-Eoan

发明人： Lew G. Chua-Eoan

IPC分类号： H03K3/037 ,  H03K3/289

CPC分类号： G11C11/16 ,  G11C11/005 ,  G11C14/0081

摘要： Electronic circuits use latches including a magnetic tunnel junction (MTJ) structure and logic circuitry arranged to produce a selective state in the MTJ structure. Because the selective state is maintained magnetically, the state of the latch or electronic circuit can be maintained even while power is removed from the electronic device.

摘要翻译： 电子电路使用包括磁隧道结（MTJ）结构的锁存器和被布置成在MTJ结构中产生选择状态的逻辑电路。 由于选择状态是以磁性方式保持的，所以即使从电子设备移除电力，也可以保持闩锁或电子电路的状态。

公开(公告)号：US20100039136A1

公开(公告)日：2010-02-18

申请号：US12192386

申请日：2008-08-15

申请人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

发明人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

IPC分类号： H03K19/173

CPC分类号： G11C11/16

摘要： A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.

摘要翻译： 可再编程门逻辑并行包括多个非易失性可重新配置的基于电阻状态的存储器电路，其中电路可重新配置以实现或改变所选择的门逻辑， 可配置电阻状态的存储器电路各自适于接收逻辑输入信号。 与多个并行非易失性可重配置电阻状态存储电路串联的评估开关被配置为基于存储器电路的编程状态提供输出信号。 传感器被配置为接收输出信号并且基于输出信号和提供给传感器的参考信号来提供逻辑输出信号。 可重构逻辑可以基于使用自旋转矩传递（STT）磁性隧道结（MTJ）磁阻随机存取存储器（MRAM）作为可再编程存储器元件来实现。 逻辑配置在没有电源的情况下保留。

公开(公告)号：US09048112B2

公开(公告)日：2015-06-02

申请号：US12825937

申请日：2010-06-29

申请人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H01R12/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/64 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/02 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02371 ,  H01L2224/05624 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/11 ,  H05K1/165 ,  H05K1/181 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

摘要翻译： 堆叠式集成电路包括第一层IC和第二层IC。 第一层IC和第二层IC的主动面相互面对。 互连结构，例如microbumps，将第一层IC耦合到第二层IC。 电压调节器的有源部分集成在第一半导体IC中并耦合到嵌入在其上安装有堆叠IC的封装衬底中的无源组件（例如，电容器或电感器）。 无源部件可以是在封装衬底中的多个通孔，为电压调节器的有源部分提供电感。 通过将封装衬底中的通孔耦合到安装有封装衬底的印刷电路板中的通孔，增加了提供给电压调节器的有源部分的电感。

公开(公告)号：US08692368B2

公开(公告)日：2014-04-08

申请号：US13367932

申请日：2012-02-07

申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H01L23/34

CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

摘要： A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.

摘要翻译： 堆叠集成电路（IC）装置包括具有有源面的半导体IC和互连结构。 主动面从电压调节器（MEG）接收稳压电压。 将调节电压提供给半导体IC的VREG的有效部分耦合到互连结构。 包装衬底包括一个或多个包括第一组通孔的电感器。 第一组通孔耦合到互连结构并与有源部分配合以提供用于半导体IC的调节电压。 IC还包括耦合到封装基板的印刷电路板（PCB）。 PCB包括耦合到第一组通孔的第二组通孔。 IC还包括PCB上的一个或多个导电路径。 导电路径将第二组通孔的至少两个通孔耦合在一起。

公开(公告)号：US08193630B2

公开(公告)日：2012-06-05

申请号：US13006709

申请日：2011-01-14

申请人： Lew G. Chua-Eoan ,  Thomas R. Toms ,  Boris Dimitrov Andreev ,  Justin Joseph Rosen Gagne ,  Chunlei Shi

发明人： Lew G. Chua-Eoan ,  Thomas R. Toms ,  Boris Dimitrov Andreev ,  Justin Joseph Rosen Gagne ,  Chunlei Shi

IPC分类号： H01L23/52

CPC分类号： H03K17/223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.

摘要翻译： 在一个具体实施例中，集成电路包括电气和物理耦合到封装的封装和衬底。 封装包括第一封装 - 衬底连接，第二封装 - 衬底连接以及将第一封装 - 衬底连接耦合到第二封装 - 衬底连接的金属化。 衬底经由第一封装 - 衬底连接和第二封装 - 衬底连接耦合到封装。 基板包括多个电力域和功率控制单元。 封装的第二封装 - 衬底连接耦合到多个电源域的特定电源域。 功率控制单元包括逻辑和开关，其中开关包括耦合到电压源端子的第一端子，耦合到逻辑电路的控制端子和耦合到封装的第一封装 - 衬底连接的第二端子。 逻辑选择性地激活开关以通过封装的金属化分配功率到特定的功率域。

公开(公告)号：US08143952B2

公开(公告)日：2012-03-27

申请号：US12576033

申请日：2009-10-08

申请人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

发明人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

IPC分类号： H03F3/14

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

摘要翻译： 公开了三维片上电感器，变压器和射频放大器。 射频放大器包括一对变压器和晶体管。 变压器包括至少两个电感耦合电感器。 电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔 以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。 电感器可以具有对称或不对称的几何形状。 第一金属层可以是芯片的后端部分中的金属层。 第二金属层可以位于芯片的再分布设计层中。

公开(公告)号：US20110317387A1

公开(公告)日：2011-12-29

申请号：US12825937

申请日：2010-06-29

申请人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H05K7/06 ,  H01L23/48 ,  H01L29/92 ,  H01L29/86 ,  H01L25/16 ,  H01L21/50

CPC分类号： H01L23/5384 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/02 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02371 ,  H01L2224/05624 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/11 ,  H05K1/165 ,  H05K1/181 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

摘要翻译： 堆叠式集成电路包括第一层IC和第二层IC。 第一层IC和第二层IC的主动面相互面对。 互连结构，例如microbumps，将第一层IC耦合到第二层IC。 电压调节器的有源部分集成在第一半导体IC中并耦合到嵌入在其上安装有堆叠IC的封装衬底中的无源组件（例如，电容器或电感器）。 无源部件可以是在封装衬底中的多个通孔，为电压调节器的有源部分提供电感。 通过将封装衬底中的通孔耦合到安装有封装衬底的印刷电路板中的通孔，增加了提供给电压调节器的有源部分的电感。

公开(公告)号：US08081037B2

公开(公告)日：2011-12-20

申请号：US12136952

申请日：2008-06-11

申请人： Jonghae Kim ,  Lew G. Chua-Eoan ,  Matthew Nowak

发明人： Jonghae Kim ,  Lew G. Chua-Eoan ,  Matthew Nowak

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  H03L7/0995

摘要： An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series coupled delay cells. The at least one additional ring loop is coupled to the first ring loop by one or more common delay cells shared between the first ring loop and the at least one additional ring loops.

摘要翻译： 公开了一种包括环形振荡器和相关方法的装置。 环形振荡器包括至少两个环形环。 第一环路环包括多个串联耦合的延迟单元。 至少一个附加环路包括多个串联耦合的延迟单元。 所述至少一个附加环路通过在所述第一环路和所述至少一个附加环路之间共享的一个或多个公共延迟单元耦合到所述第一环路。

公开(公告)号：US20110111705A1

公开(公告)日：2011-05-12

申请号：US13006709

申请日：2011-01-14

申请人： Lew G. Chua-Eoan ,  Thomas R. Toms ,  Boris Dimitrov Andreev ,  Justin Joseph Rosen Gagne ,  Chunlei Shi

发明人： Lew G. Chua-Eoan ,  Thomas R. Toms ,  Boris Dimitrov Andreev ,  Justin Joseph Rosen Gagne ,  Chunlei Shi

IPC分类号： G05F1/10 ,  H04W52/00

CPC分类号： H03K17/223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.

摘要翻译： 在一个具体实施例中，集成电路包括电气和物理耦合到封装的封装和衬底。 封装包括第一封装 - 衬底连接，第二封装 - 衬底连接以及将第一封装 - 衬底连接耦合到第二封装 - 衬底连接的金属化。 衬底经由第一封装 - 衬底连接和第二封装 - 衬底连接耦合到封装。 基板包括多个电力域和功率控制单元。 封装的第二封装 - 衬底连接耦合到多个电源域的特定电源域。 功率控制单元包括逻辑和开关，其中开关包括耦合到电压源端子的第一端子，耦合到逻辑电路的控制端子和耦合到封装的第一封装 - 衬底连接的第二端子。 逻辑选择性地激活开关以通过封装的金属化分配功率到特定的功率域。

公开(公告)号：US06574651B1

公开(公告)日：2003-06-03

申请号：US09411620

申请日：1999-10-01

申请人： Jeffrey Cui ,  Stephane Rossignol ,  Lew G. Chua-Eoan

发明人： Jeffrey Cui ,  Stephane Rossignol ,  Lew G. Chua-Eoan

IPC分类号： G06F738

CPC分类号： G06F7/5324 ,  G06F7/4991 ,  G06F7/49921

摘要： A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit.

摘要翻译： 32位值相乘的方法包括将每个被乘数分解成其16位分量。 这种方法导致处理器核心设计，允许重新使用乘法单元中的大部分逻辑。 乘法单元包括可以将各种尺寸的数据格式馈送到相同的乘法器电路的选择器。 提供多个数据转换路径并馈入单个压缩电路和单个可配置全加器电路。