公开(公告)号：US09853037B2

公开(公告)日：2017-12-26

申请号：US14949807

申请日：2015-11-23

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11551 ,  H01L27/11524

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have majority carriers of the same conductivity type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20170338412A1

公开(公告)日：2017-11-23

申请号：US15669484

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal R. Parekh

IPC: H01L45/00 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L45/16 ,  H01L21/0337 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/2472 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

公开(公告)号：US09748474B2

公开(公告)日：2017-08-29

申请号：US14524322

申请日：2014-10-27

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal R. Parekh

IPC: H01L47/00 ,  H01L45/00 ,  H01L21/033 ,  H01L21/768 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L21/0337 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/2472 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

公开(公告)号：US09741732B2

公开(公告)日：2017-08-22

申请号：US14830517

申请日：2015-08-19

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L29/76 ,  H01L27/115 ,  H01L27/02 ,  H01L27/11582 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20170148802A1

公开(公告)日：2017-05-25

申请号：US14949807

申请日：2015-11-23

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20170077067A1

公开(公告)日：2017-03-16

申请号：US15361659

申请日：2016-11-28

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative system in accordance with a particular embodiment includes a semiconductor substrate having an opening that includes a generally cylindrical portion with a generally smooth, uniform surface. The opening also includes a terminal portion extending transversely to the cylindrical portion and intersecting. A single, uniform, homogeneous volume of conductive material is disposed in both the cylindrical portion and the terminal portion of the opening, the conductive material forming a conductive path in the cylindrical portion and at least a portion of a conductive terminal in the terminal portion. The conductive terminal has a cross-section with generally flat walls aligned with crystal planes of the semiconductor substrate material. The conductive terminal projects away from the semiconductor substrate.

Abstract translation: 公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。 根据特定实施例的代表性系统包括具有开口的半导体衬底，该开口包括具有大致平滑，均匀表面的大致圆柱形部分。 开口还包括横向于圆柱形部分延伸并且相交的端子部分。 导电材料的圆柱形部分和端子部分均设置均匀的均匀体积的导电材料，导电材料在圆柱形部分中形成导电路径，并在端子部分中形成至少一部分导电端子。 导电端子具有与半导体衬底材料的晶面对准的大致平坦的壁的横截面。 导电端子远离半导体基板突出。

公开(公告)号：US09508628B2

公开(公告)日：2016-11-29

申请号：US14154329

申请日：2014-01-14

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/04 ,  H01L23/52 ,  H01L29/40 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

Abstract translation: 公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。 根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时 防止施加保护涂层的去除衬底材料。 该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。 然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

公开(公告)号：US09502516B2

公开(公告)日：2016-11-22

申请号：US14247968

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Darren V. Young ,  Kunal R. Parekh ,  Casey Smith

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/407 ,  H01L29/66621 ,  H01L29/7831

Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.

Abstract translation: 与半导体器件一起使用的嵌入式晶体管器件可以包括具有多个功函数材料的栅电极，彼此电隔离并且被提供有两个或多个电压源的材料，或者在栅电极内产生二极管结的材料。

公开(公告)号：US09449906B2

公开(公告)日：2016-09-20

申请号：US14514184

申请日：2014-10-14

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/014

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.

Abstract translation: 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括在半导体器件的前侧形成一个或多个开口，并且在部分填充开口的开口中形成牺牲塞。 该方法还包括用导电材料进一步填充部分填充的开口，其中各个牺牲插塞通常在导电材料和半导体器件的衬底之间。 牺牲插头暴露在半导体器件的背面。 可以通过去除牺牲塞在背面形成接触区域。

公开(公告)号：US20150093892A1

公开(公告)日：2015-04-02

申请号：US14563953

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/306

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

Abstract translation: 本文公开了具有贯穿衬底互连和相关制造方法的微电子器件。 在一个实施例中，半导体器件包括承载第一和第二金属化层的半导体衬底。 第二金属化层与半导体衬底间隔开，其间具有第一金属化层。 半导体器件还包括至少部分延伸穿过半导体衬底的导电互连。 第一金属化层经由第二金属化层与导电互连电接触。