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    DATA BUS INVERSION USABLE IN A MEMORY SYSTEM
    31.
    发明申请
    DATA BUS INVERSION USABLE IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20150363260A1

    公开(公告)日：2015-12-17

    申请号：US14833876

    申请日：2015-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis

    IPC: G06F11/10

    CPC classification number: G06F11/1004 ,  G06F11/1008 ,  G06F11/1048

    Abstract: Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.

    Methods and apparatuses for low-power multi-level encoded signals
    32.
    发明授权
    Methods and apparatuses for low-power multi-level encoded signals 有权
    低功率多电平编码信号的方法和装置

    公开(公告)号：US09148170B2

    公开(公告)日：2015-09-29

    申请号：US14506902

    申请日：2014-10-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Timothy M. Hollis

    IPC: H03M5/20 ,  G06F13/42 ,  H03M5/02

    CPC classification number: H03M5/20 ,  G06F13/42 ,  H03M5/02

    Abstract: Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.

    Abstract translation: 公开了用于提供多电平编码信号的方法和装置。 装置可以包括编码电路和多电平编码器。 编码电路可以被配置为至少部分地基于数据来接收数据并提供编码数据。 多电平编码器可以耦合到编码电路并且被配置为接收编码数据。 多电平编码器还可以被配置为至少部分地响应于接收编码数据而将编码数据作为多电平信号提供给总线。

    Adjustable data drivers and methods for driving data signals
    33.
    发明授权
    Adjustable data drivers and methods for driving data signals 有权
    用于驱动数据信号的可调数据驱动程序和方法

    公开(公告)号：US09065442B2

    公开(公告)日：2015-06-23

    申请号：US13945603

    申请日：2013-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Bruce W. Schober

    IPC: H03K19/094 ,  H03K19/08 ,  H03K19/00 ,  H03K19/0175

    CPC classification number: H03K19/08 ,  H03K19/0005 ,  H03K19/017581

    Abstract: Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data driver is adjusted based at least in part on the driver adjustment signal.

    Abstract translation: 公开了用于将输入数据信号驱动到信号线上作为输出数据信号的装置和方法。 示例性装置包括检测电路，驱动器调整电路和数据驱动器。 检测电路被配置为检测要驱动到相邻信号线上的一组输入数据信号的特性。 特征可以是例如用于输入数据信号组的逻辑电平和/或转换的特定组合。 驱动器调整电路被配置为至少部分地基于由检测电路提供的检测信号来提供驱动器调整信号。 数据驱动器被配置为驱动该组输入数据信号中的相应一个作为输出数据信号中的相应一个，其中至少部分地基于驾驶员调整信号来调整数据驱动器。

    SELF-CALIBRATION IN A MEMORY DEVICE
    35.
    发明申请
    SELF-CALIBRATION IN A MEMORY DEVICE 有权

    公开(公告)号：US20240420789A1

    公开(公告)日：2024-12-19

    申请号：US18638379

    申请日：2024-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

    IPC: G11C29/12 ,  G11C29/20

    Abstract: Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.

    APPARATUS WITH SPEED SELECTION MECHANISM AND METHOD FOR OPERATING
    36.
    发明公开
    APPARATUS WITH SPEED SELECTION MECHANISM AND METHOD FOR OPERATING 审中-公开

    公开(公告)号：US20240305507A1

    公开(公告)日：2024-09-12

    申请号：US18584986

    申请日：2024-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Chulkyu Lee ,  Timothy M. Hollis

    IPC: H04L25/03 ,  G06F13/16

    CPC classification number: H04L25/03267 ,  G06F13/1668 ,  H04L25/03057

    Abstract: Methods, apparatuses, and systems related to an apparatus for managing on-die inter-symbol interference (ISI) are described. The apparatus may include (1) a single communication path with a set of drivers and (2) an on-die ISI prevention circuit coupled to the communication path in parallel. The single communication path may be used to propagate a slower speed signal and a higher speed signal. The on-die ISI prevention circuit may be configured to adjust the propagated signal for one of the speeds to reduce the ISI in the communicated signal.

    APPARATUSES INCLUDING BALL GRID ARRAYS AND ASSOCIATED SYSTEMS
    37.
    发明公开
    APPARATUSES INCLUDING BALL GRID ARRAYS AND ASSOCIATED SYSTEMS 审中-公开

    公开(公告)号：US20240282691A1

    公开(公告)日：2024-08-22

    申请号：US18652515

    申请日：2024-05-01

    Applicant: Micron Technology, Inc.

    Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

    IPC: H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

    Abstract: Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

    Programmable Memory Timing
    38.
    发明公开
    Programmable Memory Timing 审中-公开

    公开(公告)号：US20240161796A1

    公开(公告)日：2024-05-16

    申请号：US18420404

    申请日：2024-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

    IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

    CPC classification number: G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

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