公开(公告)号：US20210012817A1

公开(公告)日：2021-01-14

申请号：US16508753

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Christopher Vincent Antoine Laurent ,  Andrea Martinelli

IPC: G11C7/08 ,  G06F13/16 ,  G06F3/06 ,  G11C8/08 ,  G11C8/10 ,  G11C5/14 ,  G11C7/12 ,  G11C7/10

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.

公开(公告)号：US09164894B2

公开(公告)日：2015-10-20

申请号：US14165265

申请日：2014-01-27

Applicant: Micron Technology Inc.

Inventor： Gerald Barkley ,  Sunil Shetty ,  Andrea Martinelli

IPC: G06F12/00 ,  G06F12/02 ,  G11C13/00

CPC classification number: G06F12/0246 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0088

Abstract: Subject matter disclosed herein relates to a memory device and method of programming same. In some embodiments, a memory device can be programmed by partitioning information into a plurality of chunks. Partitioning can be performed by determining a pattern of logic ones and zeroes, and setting a size of an information chunk based on the pattern of logic ones and zeroes.

Abstract translation: 本文公开的主题涉及一种对其进行编程的存储器件及其方法。 在一些实施例中，可以通过将信息划分成多个块来编程存储器设备。 可以通过确定逻辑1和零的模式来执行分区，并且基于逻辑1和零的模式来设置信息块的大小。

公开(公告)号：US20240353914A1

公开(公告)日：2024-10-24

申请号：US18762482

申请日：2024-07-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent

IPC: G06F1/3287 ,  G06F1/28 ,  G06F1/3234 ,  G11C11/22 ,  G11C11/4096

CPC classification number: G06F1/3287 ,  G06F1/28 ,  G06F1/3275 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/4096

Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

公开(公告)号：US12045113B2

公开(公告)日：2024-07-23

申请号：US16551581

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent

IPC: G06F1/3287 ,  G06F1/28 ,  G06F1/3234 ,  G11C11/22 ,  G11C11/4096

CPC classification number: G06F1/3287 ,  G06F1/28 ,  G06F1/3275 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/4096

Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

公开(公告)号：US20240071483A1

公开(公告)日：2024-02-29

申请号：US17898392

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Francesco Mastroianni ,  Andrea Martinelli ,  Efrem Bolandrina ,  Lucia Di Martino ,  Riccardo Muzzetto ,  Zhongyuan Lu ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C11/56 ,  G06F3/06 ,  G06F12/02

CPC classification number: G11C11/5628 ,  G06F3/0679 ,  G06F12/0246

Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.

公开(公告)号：US20230395136A1

公开(公告)日：2023-12-07

申请号：US18196268

申请日：2023-05-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Claudia Palattella ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/4096 ,  G11C11/4078 ,  G11C11/4099

CPC classification number: G11C11/4096 ,  G11C11/4078 ,  G11C11/4099

Abstract: Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.

公开(公告)号：US20230282270A1

公开(公告)日：2023-09-07

申请号：US17686240

申请日：2022-03-03

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4074

CPC classification number: G11C11/4082 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4074

Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US20230260576A1

公开(公告)日：2023-08-17

申请号：US17651216

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Maurizio Rizzi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3404

Abstract: Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.

公开(公告)号：US20220336015A1

公开(公告)日：2022-10-20

申请号：US17231668

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

公开(公告)号：US20220122643A1

公开(公告)日：2022-04-21

申请号：US17499303

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Christopher Vincent Antoine Laurent ,  Andrea Martinelli

IPC: G11C7/08 ,  G06F13/16 ,  G11C7/10 ,  G11C8/08 ,  G06F3/06 ,  G11C7/12 ,  G11C5/14 ,  G11C8/10

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.