公开(公告)号：US20110078511A1

公开(公告)日：2011-03-31

申请号：US12894710

申请日：2010-09-30

申请人： Nishant Sinha ,  Chao Wang

发明人： Nishant Sinha ,  Chao Wang

IPC分类号： G06F11/08 ,  G06F11/00

CPC分类号： G06F11/3604

摘要： Methods and systems for concurrent program verification. A concurrent program is summarized into a symbolic interference skeleton (IS) using data flow analysis. Sequential consistency constraints are enforced on read and write events in the IS. Error conditions are checked together with the IS using a processor.

摘要翻译： 并发程序验证的方法和系统。 使用数据流分析将并发程序总结为符号干扰骨架（IS）。 在IS中的读写事件上执行顺序一致性约束。 使用处理器与IS一起检查错误状况。

公开(公告)号：US07837805B2

公开(公告)日：2010-11-23

申请号：US11847073

申请日：2007-08-29

申请人： Gurtej S. Sandhu ,  Nishant Sinha

发明人： Gurtej S. Sandhu ,  Nishant Sinha

IPC分类号： B08B3/04 ,  B08B3/08 ,  B08B3/10

CPC分类号： H01L21/67051 ,  B08B3/02 ,  B24C1/003 ,  B24C5/005 ,  H01L21/02096

摘要： Some embodiments include methods of treating surfaces with aerosol particles. The aerosol particles may be formed as liquid particles, and then passed through a chamber under conditions which change the elasticity of the particles prior to impacting a surface with the particles. The change in elasticity may be an increase in the elasticity, or a decrease in the elasticity. The change in elasticity may be accomplished by causing a phase change of one or more components of the aerosol particles such as, for example, by at least partially freezing the aerosol particles, or by forming entrained bubbles within the aerosol particles. Some embodiments include apparatuses that may be utilized during treatment of surfaces with aerosol particles.

摘要翻译： 一些实施方案包括用气溶胶颗粒处理表面的方法。 气溶胶颗粒可以形成为液体颗粒，然后在使颗粒撞击表面之前改变颗粒的弹性的条件下通过室。 弹性的变化可能是弹性的增加或弹性的降低。 弹性变化可以通过引起气溶胶颗粒的一种或多种组分的相变，例如通过至少部分地冷冻气溶胶颗粒，或通过在气溶胶颗粒内形成夹带的气泡来实现。 一些实施方案包括在用气溶胶颗粒处理表面期间可以使用的装置。

公开(公告)号：US20100025854A1

公开(公告)日：2010-02-04

申请号：US12185675

申请日：2008-08-04

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L28/40 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76882 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

摘要翻译： 本文公开了用于从微电子衬底去除导电材料（例如贵金属）的抛光系统和方法。 所述方法的若干实施例包括在基底材料中形成孔，将导电材料设置在基底材料和孔中，并将填充材料设置在导电材料上。 填充材料至少部分地填充孔。 然后抛光衬底材料以去除导电材料和孔的外部的填充材料的至少一部分，在此期间，填充材料在抛光衬底材料期间基本上防止导电材料污染到孔中。

公开(公告)号：US20100013107A1

公开(公告)日：2010-01-21

申请号：US12174393

申请日：2008-07-16

申请人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

发明人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

摘要翻译： 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。

公开(公告)号：US20090275208A1

公开(公告)日：2009-11-05

申请号：US12114174

申请日：2008-05-02

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L21/306 ,  C23F1/12

CPC分类号： H01L21/3081 ,  H01L21/31111

摘要： Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

摘要翻译： 一些实施方案包括去除其中二氧化硅暴露于包括活性氢和至少一种伯，仲，叔或季铵卤化物的混合物的二氧化硅的方法。 混合物还可以包括铊，BX 3和PQ 3中的一种或多种，​​其中X和Q是卤化物。 一些实施方案包括相对于掺杂二氧化硅选择性地蚀刻未掺杂二氧化硅的方法，其中在蚀刻之前将铊掺入掺杂的二氧化硅中。 一些实施方案包括含有掺杂铊的二氧化硅至约1重量％至约10重量％的浓度的物质的组合物。

公开(公告)号：US07608904B2

公开(公告)日：2009-10-27

申请号：US11717294

申请日：2007-03-12

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L29/78 ,  H01L29/47

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a conductive material within the via aperture, a barrier material and solder, or a silicon-containing filler. Systems including such semiconductor device components are also disclosed.

摘要翻译： 半导体器件部件包括至少一个导电通孔。 至少一个导电通孔可以包括种子层，用于促进导电材料在通孔孔内的粘附，阻挡材料和焊料，或含硅填料。 还公开了包括这种半导体器件部件的系统。

公开(公告)号：US20090253271A1

公开(公告)日：2009-10-08

申请号：US12098124

申请日：2008-04-04

申请人： Nishant Sinha ,  Gurtej S. Sandhu ,  John Smythe

发明人： Nishant Sinha ,  Gurtej S. Sandhu ,  John Smythe

IPC分类号： H01L21/469

CPC分类号： H01L21/02282 ,  B01D19/0078 ,  B01F11/0071 ,  B05C11/02 ,  B05D1/005 ,  B05D3/12 ,  B08B3/12 ,  G03D3/04 ,  G03F7/162 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/67017 ,  H01L21/67092 ,  H01L21/6715 ,  H01L21/76819

摘要： An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure to alter the liquid topography. Other apparatus and processes are disclosed.

摘要翻译： 一种装置和方法用于将声波压力施加在展现液体形貌和溶剂蒸汽超压中以改变液体形貌的旋涂膜液体质量上。 公开了其他装置和方法。

公开(公告)号：US07345350B2

公开(公告)日：2008-03-18

申请号：US10668914

申请日：2003-09-23

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L31/00 ,  H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and the opposing, second surface. A seed layer is formed on a sidewall defining the at least one hole of the substrate and coated with a conductive layer, and a conductive or nonconductive filler material is introduced into the remaining space within the at least one hole. A method of forming a conductive via through a substrate using a blind hole is also disclosed. Semiconductor components and electronic systems having substrates including the conductive via of the present invention are also disclosed.

摘要翻译： 公开了一种在半导体部件中形成导电通孔的方法。 该方法包括提供具有第一表面和相对的第二表面的基底。 在基板上形成至少一个孔，该孔在第一表面和相对的第二表面之间延伸。 种子层形成在限定基底的至少一个孔并且涂覆有导电层的侧壁上，并且导电或非导电填充材料被引入至少一个孔内的剩余空间中。 还公开了使用盲孔通过基板形成导电通孔的方法。 还公开了具有包括本发明的导电通孔的基板的半导体元件和电子系统。

公开(公告)号：US07335935B2

公开(公告)日：2008-02-26

申请号：US11188235

申请日：2005-07-22

申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

公开(公告)号：US07316063B2

公开(公告)日：2008-01-08

申请号：US10755905

申请日：2004-01-12

申请人： Warren M. Farnworth ,  Steven M. McDonald ,  Nishant Sinha ,  William M. Hiatt

发明人： Warren M. Farnworth ,  Steven M. McDonald ,  Nishant Sinha ,  William M. Hiatt

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K3/426 ,  H01L21/486 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/4916 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

摘要： A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.

摘要翻译： 公开了一种制造衬底的方法。 孔径形成在基板坯件中。 导电层形成在基板的相对表面上以及孔内。 通过掩模和蚀刻在一个或两个相对的表面上限定导电元件。 可以使用附加的导电材料层来提供用于导电元件的阻挡层和贵金属盖。 本发明的方法可用于制造用于封装半导体器件或测试基板的插入器。 还公开了底物前体结构。