公开(公告)号：US07053471B2

公开(公告)日：2006-05-30

申请号：US10267784

申请日：2002-10-10

申请人： Tamaki Wada ,  Hirotaka Nishizawa ,  Masachika Masuda ,  Kenji Osawa ,  Junichiro Osako ,  Satoshi Hatakeyama ,  Haruji Ishihara ,  Kazuo Yoshizaki ,  Kazunori Furusawa

发明人： Tamaki Wada ,  Hirotaka Nishizawa ,  Masachika Masuda ,  Kenji Osawa ,  Junichiro Osako ,  Satoshi Hatakeyama ,  Haruji Ishihara ,  Kazuo Yoshizaki ,  Kazunori Furusawa

IPC分类号： H01L23/02 ,  H05K5/00

CPC分类号： G06K19/077 ,  G06K19/07732 ,  G06K19/07737 ,  G06K19/07739 ,  G06K19/07743 ,  G11C5/04 ,  H01L23/5388 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H05K5/026 ,  H05K5/0282 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

摘要翻译： 在具有形成在小型存储卡1的盖3上的突出横截面的适配器安装部分3a上，适配器2侧的凹部装配成两个部分作为整体单元形成在 因此，小型存储卡1可以保持与现有存储卡的尺寸兼容性，由此小型存储卡1也可以用于设计为处理现有存储卡的设备中。

公开(公告)号：US06885092B1

公开(公告)日：2005-04-26

申请号：US09453171

申请日：1999-12-02

申请人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

发明人： Kazuki Sakuma ,  Masayasu Kawamura ,  Yasushi Takahashi ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano

IPC分类号： G11C8/00 ,  H01L23/02 ,  H01L23/495 ,  H01L23/28 ,  H01L23/04 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

摘要翻译： 半导体器件通过层叠两个半导体芯片与其背面面对面设置而形成。 每个半导体芯片设置有用于时钟使能的外部引线，时钟使能信号和芯片选择信号被单独地输入。 在访问一个半导体芯片的情况下，通过将时钟使能信号和芯片选择信号设置为非活动状态，将另一个半导体芯片设置为低功耗模式。

公开(公告)号：US06750080B2

公开(公告)日：2004-06-15

申请号：US10372136

申请日：2003-02-25

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Tomoko Higashino ,  Takafumi Nishita ,  Hiroshi Ohno

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Tomoko Higashino ,  Takafumi Nishita ,  Hiroshi Ohno

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/01026 ,  H01L2224/48227 ,  H01L2924/3512 ,  H01L2924/00012

摘要： Two semiconductor chips are bonded to each other with the rear surfaces of the respective semiconductor chips faced to each other, so that two longer sides of the semiconductor chips may confront the side of leads, and supporting leads are bonded and fixed onto the circuit forming surface of one of the semiconductor chips. The semiconductor chips are further bonded to each other in a state where the positions of the respective semiconductor chips are staggered relative to each other so that electrodes of one semiconductor chip may lie outside the other longer side of the other semiconductor chip, and that electrodes of the second semiconductor chip may lie outside the other longer side of the first semiconductor chip.

摘要翻译： 两个半导体芯片彼此接合，各半导体芯片的后表面彼此面对，使得半导体芯片的两个较长的侧面可以面对引线的侧面，并且支撑引线被接合并固定到电路形成表面 的其中一个半导体芯片。 半导体芯片在各半导体芯片的位置相对于彼此交错的状态下进一步接合，使得一个半导体芯片的电极可以位于另一半导体芯片的另一个较长侧的外侧，并且， 第二半导体芯片可以位于第一半导体芯片的另一长边的外侧。

公开(公告)号：US06555918B2

公开(公告)日：2003-04-29

申请号：US10103775

申请日：2002-03-25

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

摘要： A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

公开(公告)号：US06410987B1

公开(公告)日：2002-06-25

申请号：US09450676

申请日：1999-11-30

申请人： Kouichi Kanemoto ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Mikako Kimura

发明人： Kouichi Kanemoto ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Mikako Kimura

IPC分类号： H01L2348

CPC分类号： H01L21/6836 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68327 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01028 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.

公开(公告)号：US06392295B1

公开(公告)日：2002-05-21

申请号：US09421274

申请日：1999-10-20

申请人： Akihiko Iwaya ,  Tamaki Wada ,  Masachika Masuda

发明人： Akihiko Iwaya ,  Tamaki Wada ,  Masachika Masuda

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/48647 ,  H01L2224/4866 ,  H01L2224/48699 ,  H01L2224/48747 ,  H01L2224/4876 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85447 ,  H01L2224/8546 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

公开(公告)号：US06383845B2

公开(公告)日：2002-05-07

申请号：US09854626

申请日：2001-05-15

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Hirotaka Nishizawa ,  Toshio Sugano ,  Yasushi Takahashi ,  Masayasu Kawamura

IPC分类号： H01L2144

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

摘要： A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

摘要翻译： 一种半导体器件，包括树脂模具，位于树脂模具内部的两个半导体芯片，具有形成在前表面上的前后表面和外部端子以及从树脂模具的内部延伸到外部的引线，其中每个所述引线 至少在树脂模具中分支成两个分支引线，一个分支引线固定到一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，另一个分支引线被固定到 另一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，并且两个半导体芯片彼此堆叠，并且它们的背面彼此相对。

公开(公告)号：US20110227234A1

公开(公告)日：2011-09-22

申请号：US13153384

申请日：2011-06-03

申请人： Hirotaka Nishizawa ,  Akira Higuchi ,  Kenji Osawa ,  Junichiro Osako ,  Tamaki Wada ,  Michiaki Sugiyama

发明人： Hirotaka Nishizawa ,  Akira Higuchi ,  Kenji Osawa ,  Junichiro Osako ,  Tamaki Wada ,  Michiaki Sugiyama

IPC分类号： H01L23/49

CPC分类号： G06K19/077 ,  G06K19/07732 ,  H01L24/06 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes. The security process by a security controller independent interface can also be guaranteed.

摘要翻译： 多功能卡装置具有连接到接口控制器和外部连接端子的外部连接端子，接口控制器，存储器和安全控制器。 接口控制器具有多个接口控制模式，并且根据来自外部的指令通过控制模式来控制外部接口动作和存储器接口动作。 外部连接端子具有针对每个接口控制模式个性化的单个端子，以及共用公共端子。 公共端子包括时钟输入端子，电源端子和接地端子。 数据终端和安全控制器的专用终端包括在各个终端中。 外部连接终端的部分共享和个性化可以保证接口的可靠性，并且可以通过某种接口控制模式来增加对物理量的控制。 安全控制器独立接口的安全过程也可以保证。

公开(公告)号：US20100267419A1

公开(公告)日：2010-10-21

申请号：US12746918

申请日：2007-12-10

申请人： Hirotaka Nishizawa ,  Hironori Iwasaki ,  Hideo Koike ,  Junichiro Osako ,  Tamaki Wada ,  Takashi Totsuka

发明人： Hirotaka Nishizawa ,  Hironori Iwasaki ,  Hideo Koike ,  Junichiro Osako ,  Tamaki Wada ,  Takashi Totsuka

IPC分类号： H04W88/02

CPC分类号： G06K7/0021 ,  G06K7/10237 ,  G06K19/07 ,  G06K19/07732 ,  G06K19/07741 ,  G06K19/07769 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01R31/06 ,  H05K5/0282 ,  H01L2924/00014 ,  H01L2924/00012

摘要： In an IC card, there is provided a technique capable of large expandability of a memory volume, and a memory volume and a cost matched with a user's requirement. A SIM adapter 101 has a top panel 104 for covering a recess portion. In the top panel 104, when a memory card 103 is not inserted, the top panel 104 is positioned at a first height, and, when the memory card 103 is inserted, a part of the top panel 104 is engaged with a part of the SIM adapter 101 so that the top panel is latched at a second height higher than the first height. Also, into a SIM adapter, a top panel for fixing a memory card when the memory card is inserted is inserted, and a part of the top panel is engaged with a part of the SIM adapter so that the top panel is latched when the memory card is inserted. Further, into a SIM adapter, a top panel for fixing a memory card when the memory card is inserted is inserted, and the top panel has a terminal strip contacting with both of a terminal of the SIM adapter and a terminal of the memory card so that the terminal strip electrically connects between both of them.

摘要翻译： 在IC卡中，提供了一种能够大容量地扩展存储器容量以及与用户需求相匹配的存储器容量和成本的技术。 SIM适配器101具有用于覆盖凹部的顶板104。 在顶板104中，当没有插入存储卡103时，顶板104位于第一高度，并且当插入存储卡103时，顶板104的一部分与一部分 SIM适配器101，使得顶板在比第一高度高的第二高度处被闩锁。 另外，在SIM卡适配器中，插入存储卡时用于固定存储卡的顶板被插入，并且顶板的一部分与SIM适配器的一部分接合，使得顶板在存储器 插入卡。 此外，在SIM适配器中，插入存储卡时用于固定存储卡的顶板，并且顶板具有与SIM适配器的端子和存储卡的端子两者接触的端子排，因此 端子条在它们之间电连接。

公开(公告)号：US07549593B2

公开(公告)日：2009-06-23

申请号：US10550578

申请日：2004-09-24

申请人： Hirotaka Nishizawa ,  Kenji Osawa ,  Hideo Koike ,  Junichiro Osako ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Kenji Osawa ,  Hideo Koike ,  Junichiro Osako ,  Tamaki Wada

IPC分类号： G06K19/06

CPC分类号： G06K19/07732 ,  G06K7/0013 ,  G06K7/0069 ,  G06K19/07743

摘要： A semiconductor device includes external interface terminals and processing circuits, and it is fed with an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for, at least, a predetermined time period since the separation of an extraction detecting terminal among the external interface terminals, from the corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. The processing circuits include an interface control circuit (2) which is connected to the external interface terminals, and a rewritable nonvolatile memory (3) which is controlled by the interface control circuit. The nonvolatile memory stores information on the basis of the difference of the threshold voltages of memory cells. The interface control circuit causes a storage area midway of a threshold voltage initialization process to complete a process in which the threshold voltages of the memory cells are uniformalized into a predetermined threshold voltage distribution, before the power source is cut off after the separation of the extraction detecting terminal from the corresponding terminal of the host equipment.

摘要翻译： 半导体器件包括外部接口端子和处理电路，并且当可拆卸地设置在主机设备中时，其被馈送有工作电源。 外部接口端子之间的电源馈送端子（VCC，VSS）足够长以至少在从外部接口端子之间分离提取检测端子至少预定的时间段内接触主机设备的相应端子， 从主机设备的相应终端，它们形成为比提取检测终端在半导体器件的提取方向上更长。 处理电路包括连接到外部接口端子的接口控制电路（2）和由接口控制电路控制的可重写非易失性存储器（3）。 非易失性存储器基于存储单元的阈值电压的差来存储信息。 接口控制电路使阈值电压初始化处理的中间的存储区域完成将分离提取之前的电源切断之前将存储单元的阈值电压均匀化为规定的阈值电压分布的处理 从主机设备的相应终端检测终端。