公开(公告)号：US11742329B2

公开(公告)日：2023-08-29

申请号：US17399233

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Kyungsuk Oh ,  Hyunki Kim ,  Yongkwan Lee ,  Sangsoo Kim ,  Seungkon Mok ,  Junyoung Oh ,  Changyoung Yoo

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/16 ,  H01L23/3185 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48227

Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

公开(公告)号：US11688656B2

公开(公告)日：2023-06-27

申请号：US17098748

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/0657

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US11610975B2

公开(公告)日：2023-03-21

申请号：US17470102

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Byounghoon Lee ,  Seungkeun Cha ,  Wandon Kim

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L29/10

Abstract: Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

公开(公告)号：US11563501B2

公开(公告)日：2023-01-24

申请号：US17297948

申请日：2019-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Kim ,  Myungjin Kang ,  Hyungjoon Yu ,  Jongho Park ,  Seonghyeon Lee

IPC: H04B17/21 ,  H04B17/318

Abstract: According to various embodiments, an electronic device may comprise: a communication circuit which comprises a first antenna component and a second antenna component to determine a first value through the first antenna component and determine a second value through the second antenna component; a processor; and at least one memory, wherein the at least one memory has instructions stored therein which cause, when executed, the processor to: determine whether a first module disposed in the vicinity of the first antenna component has started operating; compensatively adjust a first value obtained during the operation of the first module, by using a first value obtained before the operation of the first module or a second value obtained during the operation of the first module, in response to the determination as to whether the first module has started operating; and operate the communication circuit according to a first value obtained by the compensation, wherein the first value obtained during the operation of the first module may contain a first noise value resulting from the operation of the first module. Various other embodiments are also possible.

公开(公告)号：US11296078B2

公开(公告)日：2022-04-05

申请号：US16431079

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.

公开(公告)号：US11217677B2

公开(公告)日：2022-01-04

申请号：US16584464

申请日：2019-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3215 ,  H01L21/3115

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US20210066046A1

公开(公告)日：2021-03-04

申请号：US16883392

申请日：2020-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Jaeho Kwak ,  Boeun Jang ,  Seokyeon Hwang ,  Yongseok Seo ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee ,  Jongho Lee ,  Daewook Kim ,  Wonpil Lee ,  Changkyu Choi

IPC: H01J37/32 ,  H01L21/67 ,  H01J37/34

Abstract: A surface treatment apparatus and a surface treatment system having the same are disclosed. The surface treatment apparatus includes a process chamber in which the surface treatment process is conducted, a plasma generator for generating process radicals as a plasma state for the surface treatment process, the plasma generator being positioned outside of the process chamber and connected to the process chamber by a supply duct, a heat exchanger arranged on the supply duct and cooling down temperature of the process radicals passing through the supply duct and a flow controller controlling the process radicals to flow out of the process chamber. The flow controller is connected to a discharge duct through which the process radicals are discharged outside the process chamber. The plasma surface treatment process is conducted to the package structure having minute mounting gap without the damages to the IC chip and the board.

公开(公告)号：US12087650B2

公开(公告)日：2024-09-10

申请号：US18315558

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/0657

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US20240250144A1

公开(公告)日：2024-07-25

申请号：US18585978

申请日：2024-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US11996365B2

公开(公告)日：2024-05-28

申请号：US18114358

申请日：2023-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Seung Hwan Kim ,  Jun Young Oh ,  Kyong Hwan Koh ,  Sangsoo Kim ,  Dong-Ju Jang

IPC: H01L23/538 ,  H01L23/16 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/16 ,  H01L23/31 ,  H01L23/5385 ,  H01L25/0652

Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.