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    Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same
    31.
    发明授权
    Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same 有权

    公开(公告)号：US12207459B2

    公开(公告)日：2025-01-21

    申请号：US17498100

    申请日：2021-10-11

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yuki Mizutani ,  Fumiaki Toyama ,  Masaaki Higashitani

    IPC: H10B41/27 ,  G11C5/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H10B43/27

    Abstract: A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.

    Modelling and prediction of virtual inline quality control in the production of memory devices
    33.
    发明授权
    Modelling and prediction of virtual inline quality control in the production of memory devices 有权

    公开(公告)号：US12135542B2

    公开(公告)日：2024-11-05

    申请号：US17979142

    申请日：2022-11-02

    Applicant: SanDisk Technologies LLC

    Inventor： Tsuyoshi Sendoda ,  Yusuke Ikawa ,  Nagarjuna Asam ,  Kei Samura ,  Masaaki Higashitani

    IPC: G05B19/418

    Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

    Semiconductor die containing silicon nitride stress compensating regions and method for making the same
    39.
    发明授权
    Semiconductor die containing silicon nitride stress compensating regions and method for making the same 有权

    公开(公告)号：US11430745B2

    公开(公告)日：2022-08-30

    申请号：US16806087

    申请日：2020-03-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

    IPC: H01L23/00 ,  H01L25/065 ,  H01L21/02

    Abstract: A method of forming a semiconductor structure includes forming first semiconductor devices over a first substrate, forming a first dielectric material layer over the first semiconductor devices, forming vertical recesses in the first dielectric material layer, such that each of the vertical recesses vertically extends from a topmost surface of the first dielectric material layer toward the first substrate, forming silicon nitride material portions in each of the vertical recesses; and locally irradiating a second subset of the silicon nitride material portions with a laser beam. A first subset of the silicon nitride material portions that is not irradiated with the laser beam includes first silicon nitride material portions that apply tensile stress to respective surrounding material portions, and the second subset of the silicon nitride material portions that is irradiated with the laser beam includes second silicon nitride material portions that apply compressive stress to respective surrounding material portions.

    Ferroelectric memory devices with dual dielectric confinement and methods of forming the same
    40.
    发明授权
    Ferroelectric memory devices with dual dielectric confinement and methods of forming the same 有权

    公开(公告)号：US11335790B2

    公开(公告)日：2022-05-17

    申请号：US16577176

    申请日：2019-09-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Peter Rabkin ,  Masaaki Higashitani

    IPC: H01L29/51 ,  H01L27/11514 ,  H01L21/28 ,  H01L29/417

    Abstract: A semiconductor structure contains a semiconductor channel extending between a source region and a drain region, at least one gate electrode, a ferroelectric material portion located between the semiconductor channel and the at least one gate electrode, a front-side gate dielectric located between the ferroelectric material portion and the semiconductor channel, and a backside gate dielectric located between the ferroelectric material portion and the at least one gate electrode. The front-side gate dielectric and the backside gate dielectric have a dielectric constant greater than 7.9 and a band gap greater than a band gap of the ferroelectric material portion.

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