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    Page buffer circuit and memory device including the same
    32.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US12073909B2

    公开(公告)日：2024-08-27

    申请号：US18085963

    申请日：2022-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

    IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C16/34

    CPC classification number: G11C7/065 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/3404

    Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

    Page buffer circuit and memory device including the same
    33.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US11842790B2

    公开(公告)日：2023-12-12

    申请号：US18125260

    申请日：2023-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

    IPC: G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

    Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

    MOLDING APPARATUS OF SEMICONDUCTOR PACKAGE
    34.
    发明公开
    MOLDING APPARATUS OF SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20230395403A1

    公开(公告)日：2023-12-07

    申请号：US18134718

    申请日：2023-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo Park ,  Myungsung Kang ,  Jaekyung Yoo ,  Unbyoung Kang ,  Chungsun Lee

    IPC: H01L21/67

    CPC classification number: H01L21/67126

    Abstract: A molding apparatus for a semiconductor package includes a chamber including a lower mold configured to hold a substrate including a plurality of molding targets, an upper mold configured to move up and down with respect to the lower mold and define a cavity between the upper mold and the lower mold, and a port configured to provide a passage communicating with the cavity, a molding material supplier configured to supply a molding material to the port, a plunger configured to pressurize the molding material inside the port, a plunger actuator configured to apply a first pressure to the plunger such that the molding material provided in the port is supplied to the cavity, and a mold actuator configured to control actuation of the upper mold. The plunger actuator is configured to supply the molding material to the cavity by applying the first pressure to the plunger, and the mold actuator is configured to pressurize the molding material in the cavity by applying a second pressure to the upper mold. The mold apparatus further includes a controller configured to control the plunger actuator to reduce the first pressure applied to the plunger after the mold actuator begins applying the second pressure to the upper mold.

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