公开(公告)号：US11710741B2

公开(公告)日：2023-07-25

申请号：US17243943

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/0337 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US20230049858A1

公开(公告)日：2023-02-16

申请号：US17720741

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Keun Hwi Cho ,  Daewon Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

公开(公告)号：US11069818B2

公开(公告)日：2021-07-20

申请号：US16435657

申请日：2019-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Geum Jong Bae ,  Kwan Young Chun

IPC: H01L29/786 ,  H01L27/092 ,  H01L27/11 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

公开(公告)号：US10790368B2

公开(公告)日：2020-09-29

申请号：US16275675

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Myung Gil Kang ,  Kang Ill Seo ,  Seon Bae Kim ,  Yong Hee Park

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L23/522

Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.

公开(公告)号：US20200091152A1

公开(公告)日：2020-03-19

申请号：US16405174

申请日：2019-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US10410931B2

公开(公告)日：2019-09-10

申请号：US15837613

申请日：2017-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil Kang ,  Hyun Seung Song ,  Sang Woo Lee

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/423

Abstract: A fabricating method of a nanosheet transistor includes: forming a plurality of sacrificial layers and a plurality of channel layers on a substrate, wherein the sacrificial layers and the channel layers are alternately arranged; forming a plurality of gates on an uppermost channel layer, wherein the gates are spaced apart from each other; forming a mask on each of the gates; selectively etching the sacrificial layers between the gates, wherein the sacrificial layers between the gates are removed by the etching; depositing a spacer material along sidewalls of the gates and in areas from which the sacrificial layers have been removed; and etching the spacer material to form sidewall spacers along the sidewalls of the gates and inner spacers between the channel layers.

公开(公告)号：US20180197794A1

公开(公告)日：2018-07-12

申请号：US15837613

申请日：2017-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil Kang ,  Hyun Seung Song ,  Sang Woo Lee

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L21/265

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78654 ,  H01L29/78696

Abstract: A fabricating method of a nanosheet transistor includes: forming a plurality of sacrificial layers and a plurality of channel layers on a substrate, wherein the sacrificial layers and the channel layers are alternately arranged; forming a plurality of gates on an uppermost channel layer, wherein the gates are spaced apart from each other; forming a mask on each of the gates; selectively etching the sacrificial layers between the gates, wherein the sacrificial layers between the gates are removed by the etching; depositing a spacer material along sidewalls of the gates and in areas from which the sacrificial layers have been removed; and etching the spacer material to form sidewall spacers along the sidewalls of the gates and inner spacers between the channel layers.

公开(公告)号：US09905645B2

公开(公告)日：2018-02-27

申请号：US15256136

申请日：2016-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil Kang ,  Seung Han Park ,  Yong Hee Park ,  Sang Hoon Baek ,  Sang Woo Lee ,  Keon Yong Cheon ,  Sung Man Whang

IPC: H01L21/336 ,  H01L29/778 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/7851

Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.

公开(公告)号：US09252274B2

公开(公告)日：2016-02-02

申请号：US14579222

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7856

Abstract: A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

公开(公告)号：US20150108545A1

公开(公告)日：2015-04-23

申请号：US14579222

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7856

Abstract: A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

Abstract translation: 场效应晶体管（FET）结构可以包括在鳍的相应不同轴向取向表面上的具有第一晶格常数和至少两个不同晶格常数层的衬底上的鳍，其中所述至少两个不同的晶格常数层各自包括晶格 与第一晶格常数不同的常数和彼此。