公开(公告)号：US09378838B2

公开(公告)日：2016-06-28

申请号：US14257335

申请日：2014-04-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/04 ,  G11C16/30 ,  G11C5/14 ,  G11C16/08 ,  G11C11/56

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

Abstract translation: 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压，并由接收第一电压的电压调节器产生。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 电压调节器由控制器使能。

公开(公告)号：US20160181517A1

公开(公告)日：2016-06-23

申请号：US14582089

申请日：2014-12-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do ,  Hieu Van Tran ,  Hung Quoc Nguyen

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/16 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/50 ,  G11C2213/52 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1273 ,  H01L45/146

Abstract: A memory device (and method of making and using the memory device) includes a first electrode of conductive material, a second electrode of conductive material, and a layer transition metal oxide material that includes first and second elongated portions meeting each other at a sharp corner. Each of the first and second elongated portions is disposed between and in electrical contact with the first and second electrodes.

Abstract translation: 存储器件（以及制造和使用存储器件的方法）包括导电材料的第一电极，导电材料的第二电极和层过渡金属氧化物材料，其包括在锐角处相互相遇的第一和第二细长部分 。 第一和第二细长部分中的每一个设置在第一和第二电极之间并与之电接触。

公开(公告)号：US09361995B1

公开(公告)日：2016-06-07

申请号：US14602262

申请日：2015-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C17/06 ,  G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/04 ,  H01L27/11521

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

公开(公告)号：US09286982B2

公开(公告)日：2016-03-15

申请号：US14455698

申请日：2014-08-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do ,  Vipin Tiwari

IPC: G11C16/14 ,  G11C16/16 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/26 ,  H01L29/423 ,  H01L27/115 ,  G11C5/02

CPC classification number: G11C16/0433 ,  G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/102 ,  G11C16/14 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L29/42328

Abstract: The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.

Abstract translation: 本发明涉及具有EEPROM功能的闪速存储器件。 闪存器件是字节可擦除和位可编程的。

公开(公告)号：US20160042790A1

公开(公告)日：2016-02-11

申请号：US14455698

申请日：2014-08-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do ,  Vipin Tiwari

IPC: G11C16/04 ,  G11C16/24 ,  H01L27/115 ,  G11C16/10 ,  G11C16/26 ,  H01L29/423 ,  G11C16/08 ,  G11C16/14

CPC classification number: G11C16/0433 ,  G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/102 ,  G11C16/14 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L29/42328

Abstract: The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.

Abstract translation: 本发明涉及具有EEPROM功能的闪速存储器件。 闪存器件是字节可擦除和位可编程的。

公开(公告)号：US09093161B2

公开(公告)日：2015-07-28

申请号：US13830207

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

Abstract translation: 公开了用于编程高级纳米闪存单元的改进的方法和装置。

公开(公告)号：US20150155039A1

公开(公告)日：2015-06-04

申请号：US14094595

申请日：2013-12-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC: G11C16/08

CPC classification number: G11C16/08 ,  G11C7/1045 ,  G11C7/1057 ,  G11C16/04 ,  G11C2207/105 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A three-dimensional NOR flash memory system is disclosed. The system optionally comprises configurable standard pins, a configurable output buffer, and a configurable input buffer.

Abstract translation: 公开了一种三维NOR闪存系统。 该系统可选地包括可配置标准引脚，可配置输出缓冲器和可配置输入缓冲器。

公开(公告)号：US20140226409A1

公开(公告)日：2014-08-14

申请号：US14257335

申请日：2014-04-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

Abstract translation: 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压，并由接收第一电压的电压调节器产生。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 电压调节器由控制器使能。

公开(公告)号：US10460810B2

公开(公告)日：2019-10-29

申请号：US15687191

申请日：2017-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/04 ,  G11C16/12 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

公开(公告)号：US10312248B2

公开(公告)日：2019-06-04

申请号：US14935201

申请日：2015-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11521 ,  G11C16/14 ,  G11C16/26 ,  H01L29/423 ,  H01L29/788

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.