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    Bond Features For Reducing Non-Bond and Methods of Forming the Same
    31.
    发明申请
    Bond Features For Reducing Non-Bond and Methods of Forming the Same 有权

    公开(公告)号：US20250006677A1

    公开(公告)日：2025-01-02

    申请号：US18342231

    申请日：2023-06-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yan-Zuo Tsai

    IPC: H01L23/00

    Abstract: A method includes depositing a first dielectric layer as a first surface layer of a first package component, forming a plurality of metal pads in the first dielectric layer, depositing a second dielectric layer as a second surface layer of a second package component, and bonding the second package component to the first package component. The first dielectric layer is bonded to the second dielectric layer. At a time after the bonding, a metal pad in the plurality of metal pads has a top surface contacting a bottom surface of the second dielectric layer.

    Method for Sigulating Semiconductor Devices and Package Device Including the Semiconductor Devices
    33.
    发明公开
    Method for Sigulating Semiconductor Devices and Package Device Including the Semiconductor Devices 审中-公开

    公开(公告)号：US20240222292A1

    公开(公告)日：2024-07-04

    申请号：US18152626

    申请日：2023-01-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Ju Tsou ,  Yung-Chi Lin ,  Yi-Hsiu Chen ,  Tsang-Jiuh Wu

    IPC: H01L23/00 ,  H01L21/304 ,  H01L21/3065

    CPC classification number: H01L23/562 ,  H01L21/3043 ,  H01L21/3065

    Abstract: In an embodiment, a device includes an integrated circuit die including a first sidewall, a second sidewall, and a third sidewall, wherein the third sidewall of the integrated circuit die is connected to the first sidewall of the integrated circuit die and the second sidewall of the integrated circuit die, wherein the third sidewall of the integrated circuit die forms a chamfered corner of the integrated circuit die; a first dielectric surrounding the integrated circuit die; a semiconductor feature disposed over the integrated circuit die, wherein the semiconductor feature includes a first sidewall, a second sidewall, and a third sidewall, wherein the third sidewall of the semiconductor feature is connected to the first sidewall of the semiconductor feature and the second sidewall of the semiconductor feature and forms a chamfered corner of the semiconductor feature; and a second dielectric surrounding the semiconductor feature.

    Integrated circuit package and method
    37.
    发明授权
    Integrated circuit package and method 有权

    公开(公告)号：US11502072B2

    公开(公告)日：2022-11-15

    申请号：US16934870

    申请日：2020-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Yung-Chi Lin ,  Wen-Chih Chiou

    IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

    Integrated circuit packages and methods of forming the same
    39.
    发明授权
    Integrated circuit packages and methods of forming the same 有权

    公开(公告)号：US11145623B2

    公开(公告)日：2021-10-12

    申请号：US16441013

    申请日：2019-06-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hao Hsu ,  Yung-Chi Lin ,  Wen-Chih Chiou

    IPC: H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

    Wafer Bonding Method
    40.
    发明申请
    Wafer Bonding Method 有权

    公开(公告)号：US20210305200A1

    公开(公告)日：2021-09-30

    申请号：US17019913

    申请日：2020-09-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC: H01L23/00 ,  H01L21/3213 ,  H01L25/00 ,  H01L25/065

    Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

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