中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

51 records (took 0.018 seconds)

    Process of fabricating circuit structure
    31.
    发明授权
    Process of fabricating circuit structure 有权
    制作电路结构的过程

    公开(公告)号：US07921550B2

    公开(公告)日：2011-04-12

    申请号：US12345474

    申请日：2008-12-29

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/00

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad.

    Abstract translation: 一种形成电路结构的工艺包括首先提供第一复合层结构。 然后提供第二复合层结构。 第一复合层结构，第二介电层和第二复合层结构被按压，使得第二电路图案和独立通孔焊盘嵌入第二电介质层中，并且第二电介质层连接到第一电介质层 层。 去除第一载体衬底和第二载体衬底以暴露第一电路图案和第二电路图案。 形成穿过第二电介质层并暴露独立通孔焊盘的至少一个第一开口，并且用导电材料填充第一开口以形成连接独立通孔焊盘和第二通孔焊盘的第二导电通孔。

    CIRCUIT STRUCTURE OF CIRCUIT BOARD AND PROCESS FOR MANUFACTURING THE SAME
    32.
    发明申请
    CIRCUIT STRUCTURE OF CIRCUIT BOARD AND PROCESS FOR MANUFACTURING THE SAME 有权
    电路板的电路结构及其制造工艺

    公开(公告)号：US20100059256A1

    公开(公告)日：2010-03-11

    申请号：US12270718

    申请日：2008-11-13

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/09 ,  H05K1/00 ,  H05K3/10

    CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

    Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

    Method of manufacturing embedded wiring board
    33.
    发明授权
    Method of manufacturing embedded wiring board 有权
    嵌入式布线板的制造方法

    公开(公告)号：US09210815B2

    公开(公告)日：2015-12-08

    申请号：US13474735

    申请日：2012-05-18

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/36 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: A manufacturing method of an embedded wiring board is provided. The method includes the following steps. First, an insulation layer and a lower wiring layer are provided, wherein the insulation layer includes a polymeric material. Then, the plural catalyst grains are distributed in the polymeric material. A groove and an engraved pattern are formed on the upper surface. A blind via is formed on a bottom surface of the groove to expose the lower pad. An upper wiring layer is formed in the engraved pattern. Some catalyst grains are exposed and activated in the groove, the engraved pattern and the blind via. A first conductive pillar is formed in the groove. Finally, a second conductive pillar is formed in the blind via.

    Abstract translation: 提供了一种嵌入式布线板的制造方法。 该方法包括以下步骤。 首先，提供绝缘层和下布线层，其中绝缘层包括聚合材料。 然后，多个催化剂颗粒分布在聚合物材料中。 在上表面上形成有凹槽和雕刻图案。 在槽的底表面上形成盲孔以露出下垫。 上部布线层形成在雕刻图案中。 一些催化剂颗粒在凹槽，雕刻图案和盲孔中暴露和活化。 第一导电柱形成在凹槽中。 最后，在盲通孔中形成第二导电柱。

    CIRCUIT BOARD AND FABRICATION METHOD THEREOF
    36.
    发明申请
    CIRCUIT BOARD AND FABRICATION METHOD THEREOF 审中-公开
    电路板及其制造方法

    公开(公告)号：US20110094778A1

    公开(公告)日：2011-04-28

    申请号：US12606192

    申请日：2009-10-27

    Applicant: Cheng-Po Yu ,  Chi-Min Chang ,  Wei-Ming Cheng

    Inventor： Cheng-Po Yu ,  Chi-Min Chang ,  Wei-Ming Cheng

    IPC: H05K1/00 ,  B23K26/38

    CPC classification number: H05K3/185 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0236

    Abstract: A method for fabricating a circuit board is provided. A non-conductive material layer is provided on a core substrate, wherein the non-conductive material layer comprises a dielectric material and catalytic particles. A recessed circuit structure is then formed in the non-conductive material layer with a laser beam. Simultaneously, the catalytic particles in the recessed circuit structure are activated with aid of the laser. A buried conductive structure is then formed in the recessed circuit structure by chemical copper deposition methods.

    Abstract translation: 提供一种制造电路板的方法。 非导电材料层设置在芯基板上，其中非导电材料层包括电介质材料和催化颗粒。 然后在非导电材料层中用激光束形成凹陷的电路结构。 同时，凹陷电路结构中的催化颗粒借助于激光器被激活。 然后通过化学铜沉积方法在凹陷电路结构中形成掩埋导电结构。

    PROCESS OF FABRICATING CIRCUIT STRUCTURE
    38.
    发明申请
    PROCESS OF FABRICATING CIRCUIT STRUCTURE 有权
    制作电路结构的过程

    公开(公告)号：US20090104772A1

    公开(公告)日：2009-04-23

    申请号：US12345474

    申请日：2008-12-29

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H01L21/44 ,  H01L21/02

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad.

    Abstract translation: 一种形成电路结构的工艺包括首先提供第一复合层结构。 然后提供第二复合层结构。 第一复合层结构，第二介电层和第二复合层结构被按压，使得第二电路图案和独立通孔焊盘嵌入第二电介质层中，并且第二电介质层连接到第一电介质层 层。 去除第一载体衬底和第二载体衬底以暴露第一电路图案和第二电路图案。 形成穿过第二电介质层并暴露独立通孔焊盘的至少一个第一开口，并且用导电材料填充第一开口以形成连接独立通孔焊盘和第二通孔焊盘的第二导电通孔。

    Method of manufacturing an embedded wiring board
    39.
    发明授权
    Method of manufacturing an embedded wiring board 有权
    嵌入式布线板的制造方法

    公开(公告)号：US09131614B2

    公开(公告)日：2015-09-08

    申请号：US13620431

    申请日：2012-09-14

    Applicant: Cheng-Po Yu ,  Chai-Liang Hsu

    Inventor： Cheng-Po Yu ,  Chai-Liang Hsu

    IPC: H05K3/02 ,  H05K3/10 ,  H05K3/18 ,  H05K3/42

    CPC classification number: H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

    Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed. The activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

    Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层。 激活绝缘层包括多个催化剂颗粒，并且覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。

    CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF
    40.
    发明申请
    CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    电路结构及其制造方法

    公开(公告)号：US20140041919A1

    公开(公告)日：2014-02-13

    申请号：US13615722

    申请日：2012-09-14

    Applicant: Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    Inventor： Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    IPC: H05K1/11 ,  H05K3/10

    CPC classification number: H05K1/0221 ,  H05K3/4644 ,  Y10T29/49155

    Abstract: A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.

    Abstract translation: 电路结构包括内部电路层，第一和第二电介质层，第一和第二导电材料层以及第二和第三导电层。 第一电介质层覆盖内电路层的第一导电层，并具有第一表面和第一电路槽。 第一导电材料层设置在第一电路槽的内部。 第二导电层设置在第一表面上并且包括信号迹线和至少两个参考迹线。 第二电介质层覆盖第一表面和第二导电层，并具有第二表面和第二电路槽。 第一和第二电路槽的宽度小于参考轨迹的宽度。 第二导电材料层设置在第二电路槽的内部。 第三导电层设置在第二表面上。

Patent Agency Ranking