公开(公告)号：US20150311183A1

公开(公告)日：2015-10-29

申请号：US14287065

申请日：2014-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/16268 ,  H01L2224/32145 ,  H01L2224/32265 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

Abstract translation: 本发明提供一种制造封装结构的方法。 提供了包括多个第一管芯的阵列芯片。 提供了包括多个第二管芯的晶片。 执行包装步骤以将阵列芯片封装到晶片上，以便电连接第一管芯和第二管芯。 本发明还提供了半导体晶片和封装结构。

公开(公告)号：US20150311117A1

公开(公告)日：2015-10-29

申请号：US14791265

申请日：2015-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/302 ,  H01L21/283

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US09048223B2

公开(公告)日：2015-06-02

申请号：US14016330

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.

Abstract translation: 公开了一种具有连接到地电势的硅通孔的封装结构，包括设置在第一器件和第二器件之间的第一器件，第二器件和导电粘合剂。 第一器件包括具有前表面和后表面的衬底以及填充有形成在衬底内的导体的多个通孔硅通孔。 第一器件通过引线接合外部连接到第二器件。

公开(公告)号：US08916471B1

公开(公告)日：2014-12-23

申请号：US13975382

申请日：2013-08-26

Applicant: United Microelectronics Corp.

Inventor： Ching-Li Yang ,  Chien-Li Kuo ,  Chung-Sung Chiang ,  Yu-Han Tsai ,  Chun-Wei Kang

IPC: H01L21/44 ,  H01L29/40 ,  H01L21/768 ,  H01L23/552 ,  H01L23/538

CPC classification number: H01L21/76898 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2924/3025

Abstract: A method for forming a through silicon via for signal and a shielding structure is provided. A substrate is provided and a region is defined on the substrate. A radio frequency (RF) circuit is formed in the region on the substrate. A through silicon trench (TST) and a through silicon via (TSV) are formed simultaneously, wherein the TST encompasses the region to serve as a shielding structure for the RF circuit. A metal interconnection system is formed on the substrate, wherein the metal interconnection system comprises a connection unit that electrically connects the TSV to the RF circuit to provide a voltage signal.

Abstract translation: 提供一种用于形成用于信号的通硅通孔和屏蔽结构的方法。 提供衬底并且在衬底上限定区域。 在基板上的区域中形成射频（RF）电路。 同时形成贯通硅沟槽（TST）和贯穿硅通孔（TSV），其中TST包围用作RF电路的屏蔽结构的区域。 在基板上形成金属互连系统，其中金属互连系统包括将TSV电连接到RF电路以提供电压信号的连接单元。

公开(公告)号：US08884398B2

公开(公告)日：2014-11-11

申请号：US13854142

申请日：2013-04-01

Applicant: United Microelectronics Corp.

Inventor： Chu-Fu Lin ,  Chien-Li Kuo ,  Ching-Li Yang

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/00

CPC classification number: H01L23/5252 ,  H01L23/525 ,  H01L23/5254 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.

Abstract translation: 反熔丝编程方法包括以下步骤。 首先，提供绝缘层。 在绝缘层上限定反熔丝区域。 反熔丝嵌入在绝缘层的反熔丝区域内。 反熔丝包括至少第一导体和第二导体。 然后，通过激光去除绝缘层的一部分，以在绝缘层中形成抗熔丝开口。 第一导体的一部分和第二导体的一部分通过反熔丝开口露出。 之后，在反熔丝开口中形成凸起下的金属层，以电连接第一导体和第二导体。

公开(公告)号：US10199273B2

公开(公告)日：2019-02-05

申请号：US14997594

申请日：2016-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/06

Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

公开(公告)号：US09704841B2

公开(公告)日：2017-07-11

申请号：US14226802

申请日：2014-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L21/70 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/80896 ,  H01L2224/81895 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material.

公开(公告)号：US09698122B2

公开(公告)日：2017-07-04

申请号：US15221011

申请日：2016-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/12 ,  H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5389 ,  H01L25/065 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.

公开(公告)号：US20160336295A1

公开(公告)日：2016-11-17

申请号：US15221011

申请日：2016-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5389 ,  H01L25/065 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.

Abstract translation: 提供半导体封装结构及其制造方法。 半导体封装结构具有n个裸片的衬底和裸片堆叠，其中n≥1。 基板具有从第一侧向第二侧延伸的第一侧，第二侧和开口。 模具堆叠设置在开口中。 基板的厚度与芯片叠层的厚度基本相同。

公开(公告)号：US09478499B2

公开(公告)日：2016-10-25

申请号：US14479526

申请日：2014-09-08

Applicant: United Microelectronics Corp.

Inventor： Chien-Li Kuo

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/04 ,  H01L23/538 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5389 ,  H01L25/065 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.

Abstract translation: 提供半导体封装结构及其制造方法。 半导体封装结构具有n个裸片的衬底和裸片堆叠，其中n≥1。 基板具有从第一侧向第二侧延伸的第一侧，第二侧和开口。 模具堆叠设置在开口中。 基板的厚度与芯片叠层的厚度基本相同。