公开(公告)号：US09466694B2

公开(公告)日：2016-10-11

申请号：US15132256

申请日：2016-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.

Abstract translation: 一种用于制造MOS晶体管器件的方法包括以下步骤。 提供了至少包括形成在其中的隔离结构的基板。 接下来，在基板上形成MOS晶体管器件，MOS晶体管器件包括栅极，源极区域，漏极区域和间隔物。 在形成MOS晶体管器件之后，在栅极的漏极侧形成至少第一虚拟触点，并且形成与栅极电连接的栅极接触。 第一虚拟触点与衬底的表面间隔开并且电连接到栅极触点。

公开(公告)号：US09391196B1

公开(公告)日：2016-07-12

申请号：US14805474

申请日：2015-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor device and a manufacturing method thereof are provided. The HV MOS transistor device includes a semiconductor substrate, a gate structure, a first sub-gate structure, and a drain region. The gate structure is disposed on the semiconductor substrate. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the semiconductor substrate, the first sub-gate structure is separated from the gate structure, and the first sub-gate structure is disposed on the first region of the semiconductor substrate. The drain region is disposed in the first region of the semiconductor substrate. The drain region is electrically connected to the first sub-gate structure via a first contact structure disposed on the drain region and the first sub-gate structure.

Abstract translation: 提供高压金属氧化物半导体（HV MOS）晶体管器件及其制造方法。 HV MOS晶体管器件包括半导体衬底，栅极结构，第一子栅极结构和漏极区域。 栅极结构设置在半导体衬底上。 半导体衬底具有分别设置在栅极结构的两个相对侧上的第一区域和第二区域。 第一子栅极结构设置在半导体衬底上，第一子栅极结构与栅极结构分离，第一子栅极结构设置在半导体衬底的第一区域上。 漏极区域设置在半导体衬底的第一区域中。 漏极区域经由设置在漏极区域和第一子栅极结构上的第一接触结构电连接到第一子栅极结构。

公开(公告)号：US09196695B2

公开(公告)日：2015-11-24

申请号：US14273538

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20210119014A1

公开(公告)日：2021-04-22

申请号：US17117090

申请日：2020-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

公开(公告)号：US10340349B2

公开(公告)日：2019-07-02

申请号：US15799692

申请日：2017-10-31

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L49/02 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

公开(公告)号：US20180233556A1

公开(公告)日：2018-08-16

申请号：US15951966

申请日：2018-04-12

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L21/311 ,  H01L27/088 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US09978647B2

公开(公告)日：2018-05-22

申请号：US14980779

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823481 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31105 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/401 ,  H01L29/4966

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

公开(公告)号：US09929056B1

公开(公告)日：2018-03-27

申请号：US15359389

申请日：2016-11-22

Applicant: United Microelectronics Corp.

Inventor： Te-Chiu Tsai ,  Shih-Yin Hsiao ,  Ching-Wei Teng ,  Tun-Jen Cheng ,  Hung-Yi Tsai ,  Shan-Shi Huang

IPC: H01L21/3205 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823462 ,  H01L21/32 ,  H01L21/823456

Abstract: A method for forming gate structures for a HV device and a MV device is provided. The method includes forming a HV oxide layer on the substrate, covering a first region predetermined for forming the HV device. Further in the method, a dielectric mask is formed on a central portion of the HV oxide layer. A thermal oxidation process is performed to form a MV oxide layer on the substrate at a second region predetermined for forming the MV device, wherein peripheral portions of the HV oxide layer not covered by the dielectric mask grow thicker. The dielectric mask is removed. A conductive layer is formed over the substrate. The conductive layer, the HV oxide layer, the MV oxide layer are patterned to form the gate structures.

公开(公告)号：US20180069089A1

公开(公告)日：2018-03-08

申请号：US15799692

申请日：2017-10-31

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

公开(公告)号：US09806150B2

公开(公告)日：2017-10-31

申请号：US15587378

申请日：2017-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Su-Hwa Tsai

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/0661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/66613 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.