公开(公告)号：US20130241081A1

公开(公告)日：2013-09-19

申请号：US13422723

申请日：2012-03-16

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L25/00 ,  H01L21/60

CPC分类号： H01L24/94 ,  G11C29/006 ,  G11C29/82 ,  H01L22/22 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24147 ,  H01L2224/25175 ,  H01L2224/32145 ,  H01L2224/821 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00

摘要： A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.

摘要翻译： 主封装包括多个堆叠的半导体芯片和与不同的半导体芯片相关联的多个第一端子。 附加封装包括附加的半导体芯片和电连接到附加半导体芯片的至少一个第二端子。 附加的半导体芯片用于代替主封装中的多个半导体芯片中的一个。 主包装和附加包装被布置成根据主包装中的多个半导体芯片中的哪一个被附加的半导体芯片代替的多个相对位置关系中的一个。

公开(公告)号：US20120313259A1

公开(公告)日：2012-12-13

申请号：US13156808

申请日：2011-06-09

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/50 ,  H01L21/304

CPC分类号： H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.

摘要翻译： 分层芯片封装包括主体和布线。 主体有一个主要部分。 主要部分具有顶表面和底表面，并且包括堆叠的多个层部分。 布线包括穿过所有多个层部分的多条线。 各层部分包括半导体芯片和多个电极。 半导体芯片具有第一表面和与其相对的第二表面。 多个电极设置在半导体芯片的第一表面的一侧。 多个层部分包括两对或更多对第一和第二层部分，其中每个第一和第二层部分中的第一和第二层部分被布置成使得各个半导体芯片的第一或第二表面彼此面对。 多个电极包括多个第一连接部和多个第二连接部。 在第一层部分中，多个第一连接部分与多条线接触。 在第二层部分中，多个第二连接部分与多条线接触。

公开(公告)号：US20120187574A1

公开(公告)日：2012-07-26

申请号：US13014093

申请日：2011-01-26

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/18 ,  H01L23/49811 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/00

摘要： A memory device has a laminated chip package and a controller plate. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller plate. A plurality of opposing wiring electrodes are formed at an opposing surface of the controller plate. A plurality of outside wiring electrodes are formed on the rear side of the opposing surface. Connection electrodes connecting the opposing wiring electrodes and the outside wiring electrodes are formed on the side surface of the controller plate. The interposed chip has a plurality of interposed wiring electrodes. The plurality of interposed wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of the plurality of opposing wiring electrodes. The controller plate is laid on the interposed chip.

摘要翻译： 存储器件具有层压芯片封装和控制器板。 在层叠芯片封装中，层叠多个存储芯片。 在层压芯片封装和控制板之间层压插入的芯片。 多个相对的布线电极形成在控制器板的相对表面处。 多个外部布线电极形成在相对表面的后侧。 连接相对的布线电极和外部布线电极的连接电极形成在控制器板的侧表面上。 插入的芯片具有多个插入的布线电极。 多个插入的布线电极形成有与多个相对的布线电极的配置图案相同的共同布置图案。 控制板放置在插入的芯片上。

公开(公告)号：US20120087217A1

公开(公告)日：2012-04-12

申请号：US13279935

申请日：2011-10-24

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： G11B13/04 ,  G11B5/60 ,  G11B5/48

CPC分类号： G11B5/3163 ,  B82Y20/00 ,  G02B6/1226 ,  G11B5/105 ,  G11B5/314 ,  G11B5/6088 ,  G11B2005/0021 ,  Y10T29/49021 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49052

摘要： A thermally assisted magnetic head is formed by performing a head forming process, a mounting part forming process and a light source mounting process in that order. In the head forming process, a planned area is secured on a light source placing surface of a slider substrate, then a magnetic head part is formed on a head area other than the planned area and a spacer for securing a mounting space for the laser diode is formed on the planned area. In the mounting part forming process, a light source mounting part is formed by removing the spacer. In the light source mounting process, a laser diode is mounted on the light source mounting part formed by the mounting part forming step.

摘要翻译： 通过以该顺序执行头部成形工艺，安装部件形成工艺和光源安装工艺来形成热辅助磁头。 在头部成形处理中，将规划区域固定在滑块基板的光源放置面上，然后将磁头部形成在除了规划区域以外的头部区域上，并且用于固定激光二极管的安装空间的间隔件 在规划区域形成。 在安装部形成工序中，通过移除间隔件形成光源安装部。 在光源安装过程中，激光二极管安装在由安装部分形成步骤形成的光源安装部分上。

公开(公告)号：US20120080782A1

公开(公告)日：2012-04-05

申请号：US12896283

申请日：2010-10-01

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L25/11 ,  H01L21/98

CPC分类号： H01L25/50 ,  H01L22/22 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014

摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.

摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 第一和第二端子通过使用第一和第二层部分的电极形成。 通过层叠两个子结构（其中包括多个预备层部分的阵列），然后切割层状子结构，通过制造层状子结构来制造分层芯片封装。 分层子结构包括多个初级线，其布置在两个相邻的预分离主体之间并且将成为多根线。

公开(公告)号：US20100195262A1

公开(公告)日：2010-08-05

申请号：US12362830

申请日：2009-01-30

申请人： Yoshitaka SASAKI ,  Atsushi IIJIMA ,  Hiroshi IKEJIMA

发明人： Yoshitaka SASAKI ,  Atsushi IIJIMA ,  Hiroshi IKEJIMA

IPC分类号： H01G4/06 ,  H01M4/29

CPC分类号： H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

摘要： In a ceramic capacitor according to the present invention, the electrode strips of an internal electrode and the dielectric strips of a ceramic dielectric member are arranged perpendicularly to the surface of a substrate, and as such, the plurality of electrode strips and the plurality of dielectric strips are arranged alternately along a parallel direction relative to the substrate surface. That is, the electrode strips and the dielectric strips are multi-layered along a parallel direction relative to the substrate surface, thereby facilitating the realization of multi-layering in the ceramic capacitor by a known patterning technology.

摘要翻译： 在根据本发明的陶瓷电容器中，内部电极的电极条和陶瓷电介质部件的介质带垂直于衬底的表面设置，因此，多个电极条和多个电介质 条带相对于基板表面沿平行方向交替布置。 也就是说，电极条和介质条沿着相对于基板表面的平行方向是多层的，从而通过已知的图案化技术有助于在陶瓷电容器中实现多层。