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31.发明公开公开(公告)号：US20240014083A1
公开(公告)日：2024-01-11
申请号：US18217827
申请日：2023-07-03
发明人： Hem P. Takiar , Raj K. Bansal , Jian Wei Lim , Li Wang , Jungbae Lee
IPC分类号： H01L23/16 , H01L23/00 , H01L25/065 , H01L21/48
CPC分类号： H01L23/16 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L24/48 , H01L21/4803 , H01L24/16 , H01L2224/73265 , H01L2224/48145 , H01L2224/32145 , H01L2224/32225 , H01L2224/16227 , H01L2924/182 , H01L2225/06562 , H01L2225/06506 , H01L2224/48227 , H01L2225/0651
摘要： A method of making a semiconductor device assembly is provided. The method comprises attaching a first semiconductor device to an upper surface of a substrate and disposing a stencil over the upper surface of the substrate. The stencil includes (i) an opening and (ii) a cavity in which the first semiconductor device is disposed. The method further comprises screen-printing an epoxy material into the opening and onto the upper surface of the substrate, removing the stencil, and planarizing an upper surface of the epoxy material to form an epoxy spacer.
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公开(公告)号：US20240003768A1
公开(公告)日：2024-01-04
申请号：US18334402
申请日：2023-06-14
IPC分类号： G01L9/00 , H01L23/00 , H01L25/065 , H01L25/00
CPC分类号： G01L9/0045 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/48108 , H01L2224/73215 , H01L2225/06506 , H01L2225/0651 , H01L2225/06524 , H01L2924/1659 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2924/16151
摘要： A semiconductor device has a substrate and a first electrical component including a sensing region disposed over the substrate. The sensing region can be responsive to external stimuli, such as pressure. A cover lid is disposed over the first electrical component and extending to the substrate with an opening in the cover lid aligned over the sensing region. A gel material is disposed within the opening of the cover lid to seal the sensing region with respect to an environment condition, such as liquid. A bond wire is coupled between the first electrical component and substrate. An adhesive layer is disposed around a perimeter of the sensing area and the cover lid is bonded to the adhesive layer. A second electrical component is disposed on the substrate and the first electrical component is disposed on the second electrical component.
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公开(公告)号：US20230411374A1
公开(公告)日：2023-12-21
申请号：US18230316
申请日：2023-08-04
申请人： Guobiao ZHANG
发明人： Guobiao ZHANG
IPC分类号： H01L25/18 , G06F9/30 , G06F15/80 , G06F21/56 , G10L15/183 , G10L15/22 , H01L25/065 , G06F18/21
CPC分类号： H01L25/18 , G06F9/3001 , G06F15/803 , G06F21/561 , G10L15/183 , G10L15/22 , H01L2225/06541 , G06F18/21 , G06F2221/034 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L25/0657
摘要： A discrete three-dimensional (3-D) processor comprises a plurality of storage-processing units (SPU's), each of the SPU's comprising a non-memory circuit, at least a memory array and at least an off-die peripheral-circuit component thereof. The 3-D processor further comprises first and second dice. The first die comprises the memory arrays, whereas the second die comprises the non-memory circuit and the off-die peripheral-circuit component.
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公开(公告)号：US20230402355A1
公开(公告)日：2023-12-14
申请号：US18331215
申请日：2023-06-08
申请人： NEXPERIA B.V.
发明人： Wei Leong Tan , Wai Wai Lee , Hing Suan Cheam
IPC分类号： H01L23/495 , H01L23/367 , H01L23/31 , H01L25/065 , H01L21/52 , H01L21/56
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/3675 , H01L23/3121 , H01L25/0657 , H01L21/52 , H01L21/565 , H01L2225/06506 , H01L2021/60292
摘要： An electronic package and a method for manufacturing the same is provided. The electronic package includes a first substrate, an electronic component arranged on and/or formed in the first substrate, a thermally conductive second substrate including a first portion and a second portion integrally connected to the first portion, and at least the first portion among the first and second portion is fixedly attached to the electronic component, and a package material arranged to encapsulate the electronic component and to at least partially encapsulate the first and second substrate, and the package material includes a recess formed therein that extends up to a surface of the first portion.
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公开(公告)号：US20230387079A1
公开(公告)日：2023-11-30
申请号：US17825695
申请日：2022-05-26
发明人： Chong Leong Gan
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L25/50 , H01L2225/06506 , H01L2225/06537 , H01L2225/06562 , H01L2225/06541 , H01L2225/06586
摘要： Radiation hard semiconductor devices and packaging are disclosed. A semiconductor device assembly includes a substrate, a semiconductor die stack electrically coupled to the substrate, and an ionizing radiation shield disposed over a top die of the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC). The semiconductor device assembly further includes an encapsulant at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.
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36.发明公开公开(公告)号：US20230376432A1
公开(公告)日：2023-11-23
申请号：US18365794
申请日：2023-08-04
IPC分类号： G06F13/16 , G06F11/10 , H01L25/065
CPC分类号： G06F13/1668 , G06F11/1076 , G06F11/1004 , H01L25/0657 , H01L2225/0651 , H01L2225/06565 , H01L2225/06586 , H01L2225/06562 , H01L2225/06506 , H01L2225/06541
摘要： Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.
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公开(公告)号：US11810865B2
公开(公告)日：2023-11-07
申请号：US17381274
申请日：2021-07-21
发明人： Seungmin Kim
IPC分类号： H01L23/544 , H01L25/065 , H01L23/29 , H01L23/18
CPC分类号： H01L23/544 , H01L23/18 , H01L23/295 , H01L25/0657 , H01L2223/5442 , H01L2225/0651 , H01L2225/06506 , H01L2225/06562
摘要： A semiconductor package includes; a chip structure including vertically stacked semiconductor chips disposed on a package substrate, a spacer disposed on an uppermost semiconductor chip among the semiconductor chips, an encapsulant covering at least part of the chip structure, and including an upper portion of the encapsulant covering at least part of the spacer, and a marking pattern visually identifiable through an opening in the upper portion of the encapsulant selectively exposing portions of the spacer.
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公开(公告)号：US20230335457A1
公开(公告)日：2023-10-19
申请号：US18337975
申请日：2023-06-20
发明人： Shoucao SHI , Qiulian ZENG , Chuanming LUO , Haiping WU
IPC分类号： H01L23/367 , H01L23/498 , H01L23/00 , H01L25/07 , H01L23/31
CPC分类号： H01L23/3675 , H01L23/49844 , H01L24/48 , H01L25/072 , H01L23/3142 , H01L2224/48139 , H01L2924/1304 , H01L2924/1811 , H01L2924/183 , H01L2225/06506
摘要： A power module includes a positive input electrode, a negative input electrode, an upper bridge substrate, a lower bridge substrate, an upper bridge chip, a lower bridge chip, an output electrode, and a signal transmission terminal stacked in sequence. The upper bridge chip has a collector connected to the upper bridge substrate, and an emitter connected to the output electrode. The lower bridge chip has a collector connected to the output electrode. A sampling terminal at the emitter of the upper bridge chip, a sampling terminal at a collector of the upper bridge chip and a control terminal of the upper bridge chip, and a sampling terminal at an emitter of the lower bridge chip, a sampling terminal at a collector of the lower bridge chip, and a control terminal of the lower bridge chip are all connected to the signal transmission terminal.
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公开(公告)号：US20230335192A1
公开(公告)日：2023-10-19
申请号：US17723673
申请日：2022-04-19
IPC分类号： G11C13/00 , H01L25/065 , G11C11/16
CPC分类号： G11C13/0061 , H01L25/0657 , G11C11/1693 , H01L2225/06506 , H01L2225/06541
摘要： A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.
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公开(公告)号：US11776944B2
公开(公告)日：2023-10-03
申请号：US17994374
申请日：2022-11-27
申请人： Guobiao Zhang
发明人： Guobiao Zhang
IPC分类号： H01L25/18 , G06F9/30 , G06F15/80 , G06F21/56 , G06K9/62 , G10L15/183 , H01L25/065 , G10L15/22 , G06F18/21
CPC分类号： H01L25/18 , G06F9/3001 , G06F15/803 , G06F18/21 , G06F21/561 , G10L15/183 , G10L15/22 , H01L25/0657 , G06F2221/034 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541
摘要： A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.
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