公开(公告)号：US09947650B1

公开(公告)日：2018-04-17

申请号：US15497993

申请日：2017-04-26

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/45 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/456

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

公开(公告)号：US20180097481A1

公开(公告)日：2018-04-05

申请号：US15833039

申请日：2017-12-06

Applicant: STMicroelectronics SA

Inventor： Raphael Paulin

IPC: H03F1/56 ,  H04B5/00 ,  H03F3/195

CPC classification number: H03F1/565 ,  H03F1/086 ,  H03F1/223 ,  H03F3/195 ,  H03F2200/108 ,  H03F2200/181 ,  H03F2200/216 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/321 ,  H03F2200/336 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/75 ,  H04B5/0081

Abstract: A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.

公开(公告)号：US09911820B2

公开(公告)日：2018-03-06

申请号：US15464763

申请日：2017-03-21

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Cyrille Le Royer ,  Frederic Boeuf ,  Laurent Grenouillet ,  Louis Hutin ,  Yves Morand

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/4983 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628

Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

公开(公告)号：US09911737B2

公开(公告)日：2018-03-06

申请号：US14435004

申请日：2013-10-11

Applicant: STMicroelectronics SA ,  Commissariat àl'énergie atomique et aux énergies alternatives

Inventor： Bastien Giraud ,  Philippe Flatresse ,  Jean-Philippe Noel ,  Bertrand Pelloux-Prayer

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823892 ,  H01L27/1203

Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

公开(公告)号：US20180061838A1

公开(公告)日：2018-03-01

申请号：US15464537

申请日：2017-03-21

Applicant: STMicroelectronics SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  G11C11/409

CPC classification number: H01L27/10802 ,  G11C11/409 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/7831 ,  H01L29/7841

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US20170371099A1

公开(公告)日：2017-12-28

申请号：US15699707

申请日：2017-09-08

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/12 ,  H01S5/026 ,  H01S5/10 ,  H01S5/042 ,  H01S5/02 ,  H01S5/343

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/0422 ,  H01S5/1032 ,  H01S5/34306 ,  H01S2301/176

Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

公开(公告)号：US09853345B2

公开(公告)日：2017-12-26

申请号：US14986315

申请日：2015-12-31

Applicant: STMicroelectronics SA

Inventor： Baudouin Martineau ,  Olivier Richard ,  Frédéric Gianesello

IPC: H04B1/40 ,  H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/24 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  H03F3/20 ,  H03F3/19 ,  H03F3/21

CPC classification number: H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/211 ,  H03F3/24 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/21106 ,  H04B1/40

Abstract: A multichannel splitter formed from 1 to 2 splitters. An input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter. The 1 to 2 splitters are electrically series-connected. First respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

公开(公告)号：US09847349B1

公开(公告)日：2017-12-19

申请号：US15463493

申请日：2017-03-20

Applicant: STMicroelectronics SA

Inventor： Augustin Monroy Aguirre ,  Guillaume Bertrand ,  Philippe Cathelin ,  Raphael Paulin

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/45 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/78615

Abstract: An integrated electronic device is supported by a substrate of a silicon on insulator type. At least one transistor is formed in and on a semiconductor film of the substrate. The transistor includes a drain region and a source region of a first conductivity type and a substrate (body) region of a second conductivity type lying under a gate region. An extension region laterally continues the substrate (body) region beyond the source and drain regions and borders, in contact with, the source region through a border region having the first conductivity type. This supports formation of an electrical connection of the source region and the substrate (body) region.

公开(公告)号：US20170307468A1

公开(公告)日：2017-10-26

申请号：US15133614

申请日：2016-04-20

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Francois CARPENTIER ,  Patrick LEMAITRE ,  Jean-Robert MANOUVRIER ,  Charles BAUDOT ,  Bertrand BOROT

IPC: G01M11/02 ,  G02B6/12 ,  G02B6/28 ,  G02B6/34

CPC classification number: G01M11/02 ,  G01R31/2656 ,  G01R31/27 ,  G01R31/2884 ,  G01R31/303 ,  G01R31/311 ,  G01R31/31728 ,  G01R35/00 ,  G02B6/00 ,  G02B6/12004 ,  G02B6/2808 ,  G02B6/34

Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

公开(公告)号：US20170294379A1

公开(公告)日：2017-10-12

申请号：US15093416

申请日：2016-04-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/76877 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/0649

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.