公开(公告)号：US20030088729A1

公开(公告)日：2003-05-08

申请号：US10271352

申请日：2002-10-15

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Polizzi ,  Salvatore Poli ,  Maurizio Perroni

IPC: G06F012/00

CPC classification number: G11C7/1075 ,  G11C16/08 ,  G11C16/26 ,  G11C2207/107 ,  G11C2216/30

Abstract: A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

Abstract translation: 非易失性存储器件可以串行模式和并行模式工作。 非易失性存储器件的架构基于已经存在于标准存储器中的结构，但是包括某些修改。 这些修改包括为各种存储器访问阶段（即，写入和读取数据）添加定时状态机，以及添加内部总线和相关逻辑电路，用于在非易失性存储器中禁用标准存储器的内部地址总线 设备以串行模式运行。

公开(公告)号：US20030076718A1

公开(公告)日：2003-04-24

申请号：US10259252

申请日：2002-09-26

Applicant: STMicroelectronics S.r.I

Inventor： Paolo Rolandi

IPC: G11C007/00

CPC classification number: G11C19/282 ,  G11C11/5628 ,  G11C11/5642

Abstract: According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; ifit is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

Abstract translation: 根据多级编程方法，每个存储器位置可以以非二进制数的级编程。 要存储在两个位置中的位被分成两组，其中第一组定义高于非二进制数量级的级数。 在编程期间，如果要写入的第一组位对应于小于非二进制数量级的数字，则将第一组位写入第一位置，并将第二组位写入第二位置; 如果大于非二进制数量级，则将第一组位写入第二位置，并将第二组位写入第一位置。 第二位置中的第一组的位相对于第二组的位被存储在不同的电平。

公开(公告)号：US20030028709A1

公开(公告)日：2003-02-06

申请号：US10159780

申请日：2002-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo ,  Salvatrice Scommegna

IPC: G06F012/00

CPC classification number: G11C16/344 ,  G11C16/3436

Abstract: Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.

Abstract translation: 这里描述了一种用于电可擦除非易失性存储器件，特别是EEPROM闪存非易失性存储器件的擦除方法，其特征在于包括由排列成行和列的多个存储单元形成的存储器阵列， 子行业，其又由一行或多行形成。 存储器阵列的擦除由扇区执行，并且对于每个扇区，设想对扇区的所有存储器单元的栅极端子施加擦除脉冲，验证每个子部件的存储器单元的擦除，以及向栅极施加另外的擦除脉冲 只有子部分的存储器单元的端子不被完全擦除。

公开(公告)号：US20030027429A1

公开(公告)日：2003-02-06

申请号：US10189152

申请日：2002-07-02

Applicant: STMicroelectronics S.r.I.

Inventor： Enrico Bellandi ,  Francesco Pipia ,  Mauro Alessandri

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/02071 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76814

Abstract: The present invention relates to a process for removing post-etch residues or polymers from the surface of semiconductor devices which comprises treating the semiconductor device with an aqueous ammonia or ammonium hydroxide solution, optionally containing ozone for a time sufficient to effectively remove said post-etch residues or polymers from the surface of the semiconductor device and rinsing the semiconductor device with ozonized water, i.e. water enriched with ozone, in which water is preferably deionized (ozone-DIW).

Abstract translation: 本发明涉及用于从半导体器件表面去除蚀刻后残留物或聚合物的方法，该方法包括用氨水或氢氧化铵水溶液处理半导体器件，任选地含有臭氧足以有效去除所述后蚀刻 来自半导体器件表面的残留物或聚合物，并用臭氧化水（即，富含臭氧的水）漂洗半导体器件，其中水优选为去离子水（臭氧-DIW）。

公开(公告)号：US20030026522A1

公开(公告)日：2003-02-06

申请号：US10170020

申请日：2002-06-12

Applicant: STMicroelectronics S.r.I

Inventor： Guido Chiaretti

IPC: G02B006/26 ,  G02B006/12

CPC classification number: G02B6/3582 ,  G02B6/3538 ,  G02B6/3546 ,  G02B6/3576 ,  G02B6/3596 ,  G02B26/004

Abstract: An optical device is formed by a first chip and a second chip bonded together. The first chip (4 has an optical layer of glass housing an optical circuit; the second chip has a body of semiconductor material housing integrated electronic components and coated with a bonding layer of glass fixed directly and contiguous to the optical layer of the first chip. The bonding layer delimits cavities facing corresponding cavities in the first chip in positions corresponding to the intersection points of waveguides constituting the optical circuit. The cavities are filled with a liquid having the same refractive index as the waveguides. Underneath each cavity, in the body of semiconductor material there is present a resistor, which, when traversed by current, causes formation of a bubble inside the chamber and deflection of the light beam traversing a waveguide towards a different waveguide.

Abstract translation: 光学器件由第一芯片和第二芯片结合在一起形成。 第一芯片（4具有容纳光电路的玻璃的光学层;第二芯片具有容纳集成电子部件的半导体材料体，并且涂覆有直接固定并连续于第一芯片的光学层的玻璃结合层。 接合层在与第一芯片中相对应的腔相对应的空腔中限定了与构成光电路的波导的交点相对应的空腔，空腔中填充有与波导相同的折射率的液体，在每个腔体的下方， 半导体材料存在电阻器，当电流穿过时，电阻器在腔室内形成气泡，并且将光束穿过波导朝向不同波导的偏转。

公开(公告)号：US20030026150A1

公开(公告)日：2003-02-06

申请号：US10253217

申请日：2002-09-24

Applicant: STMicroelectronics S.r.I.

Inventor： Danilo Rimondi

IPC: G11C011/00 ,  G11C007/00

CPC classification number: G11C11/412

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided. According to the method, the level of the bit line is set in accordance with data to be written, the memory cell is precharged so as to force the output of one of the inverters of the memory cell to a predetermined logic level, and the word line is activated to couple the bit line to the memory cell.

公开(公告)号：US20030014240A1

公开(公告)日：2003-01-16

申请号：US10137109

申请日：2002-04-30

Applicant: STMicroelectronics S.r.I.

Inventor： Loris Navoni ,  Roberto Canegallo ,  Mauro Chinosi ,  Giovanni Gozzini ,  Alan Kramer ,  Pierluigi Rolandi

IPC: G06F017/21

CPC classification number: G06F17/30985 ,  G11C15/046 ,  Y10S707/961 ,  Y10S707/99945

Abstract: A memory device includes an associative memory for the storage of data belonging to a plurality of classes. The associative memory comprises a plurality of memory locations aligned along rows and columns for the storage of data along the rows. Each memory row comprises a plurality of groups of memory locations, each storing a respective datum, wherein groups of memory locations adjacent along one and the same row store data belonging to different classes. Groups of memory locations adjacent in the direction of the columns and disposed on different rows store data belonging to one and the same class. Each class comprises data having a different maximum lengths. The device is particularly suitable for the storage of words belonging to a dictionary for automatic recognition of words in a written text.

Abstract translation: 存储器装置包括用于存储属于多个类别的数据的关联存储器。 关联存储器包括沿着行和列对准的多个存储器位置，用于沿行存储数据。 每个存储器行包括多组存储器位置，每组存储相应的数据，其中沿同一行相邻的存储器位置组存储属于不同类的数据。 在列方向上相邻并且位于不同行上的存储器组的组存储属于同一类的数据。 每个类包括具有不同最大长度的数据。 该装置特别适用于存储属于用于自动识别书面文本中的词典的字典的单词。

公开(公告)号：US20020184547A1

公开(公告)日：2002-12-05

申请号：US10008586

申请日：2001-11-05

Applicant: STMicroelectronics S.r.I.

Inventor： Russell Francis ,  Michele Alia

IPC: G06F001/26 ,  G06F001/28 ,  G06F001/30

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating based upon a local clock signal. A system clock is coupled to each of the circuit blocks for providing a system clock signal thereto which functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock signal will operate as the local clock signal for selected circuit blocks. The respective circuit blocks include a local power control circuit for selectively maintaining the system clock signal as the local clock signal after the local power control receives a signal from the power control manager to shutdown this circuit block if this circuit block is currently busy when the signal to shutdown is received.

Abstract translation: 片上系统（SOC）包括掉电电路。 SOC内有几个电路块，每个电路块基于本地时钟信号进行工作。 系统时钟耦合到每个电路块，以提供系统时钟信号，其用作所选电路块的本地时钟信号。 功率控制管理器提供至少部分地确定系统时钟信号是否将作为所选电路块的本地时钟信号工作的信号。 各个电路块包括本地电源控制电路，用于在本地功率控制接收到来自功率控制管理器的信号之后选择性地将系统时钟信号保持为本地时钟信号，以在该电路块当前正在忙时关闭该电路块 收到关机。

公开(公告)号：US20020140047A1

公开(公告)日：2002-10-03

申请号：US10158424

申请日：2002-05-29

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Giuseppe Cappelletti ,  Alfonso Maurelli

IPC: H01L021/336 ,  H01L029/00 ,  H01L029/792

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/981

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.

Abstract translation: 一种用于制造集成电路的方法，该集成电路包括低工作电压，高性能逻辑电路和具有高于逻辑电路的低工作电压的高工作电压的嵌入​​式存储器件，其提供：在半导体的第一部分上 衬底，形成用于在高工作电压下工作的第一晶体管的第一栅氧化层; 在所述半导体衬底的第二部分上形成用于所述存储器件的存储器单元的第二栅氧化层; 在第一和第二栅氧化层上形成第一晶体管的第一多晶硅层栅电极和用于存储单元的浮栅电极; 在存储单元的浮栅电极上形成介电层; 在半导体衬底的第三部分上形成用于在低工作电压下工作的第二晶体管的第三栅极氧化层; 在所述电介质层和所述半导体衬底的所述第三部分上，从第二多晶硅层形成用于所述存储单元的控制栅电极和用于所述第二晶体管的栅电极; 在半导体衬底的第一部分中，形成用于第一晶体管的源区和漏区; 在半导体衬底的第二部分中，形成用于存储单元的源区和漏区; 在半导体衬底的第三部分中，形成用于第二晶体管的源区和漏极区。

公开(公告)号：US20020135062A1

公开(公告)日：2002-09-26

申请号：US10153473

申请日：2002-05-21

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Fabrizio Ghironi ,  Roberto Aina ,  Mauro Bombonati

IPC: H01L023/34

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01322

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

Abstract translation: 电连接结构，其将第一硅体与设置在第一体上的第二硅体的表面上的导电区域连接。 电连接结构包括延伸穿过第二主体的硅的至少一个插塞区域; 横向围绕所述插塞区域的至少一个绝缘区域; 以及布置在第一主体和第二主体之间并且与插头区域和第一主体的导电区域电接触的至少一个导电机电连接区域。 为了形成插塞区域，在第一晶片中挖出沟槽，并且至少部分地用绝缘材料填充沟槽。 插塞区域通过进行导致金属与硅之间的化学反应的低温热处理而固定在设置在第二晶片上的金属区域上。 将第一晶片减薄直到沟槽和电连接形成在第一晶片的自由面上。