公开(公告)号：US09923602B2

公开(公告)日：2018-03-20

申请号：US15138077

申请日：2016-04-25

Applicant: Rambus Inc.

Inventor： John W. Poulton ,  Frederick A. Ware ,  Carl W. Werner

IPC: H02H3/22 ,  H04B3/56 ,  H04L25/02 ,  G06F13/40 ,  H04B3/54 ,  H04B10/50 ,  H04B10/40 ,  H04B10/073 ,  H04B1/04

CPC classification number: H04B3/56 ,  G06F13/4072 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/15311 ,  H03F3/24 ,  H04B3/54 ,  H04B10/0731 ,  H04B10/40 ,  H04B10/50 ,  H04B2001/0408 ,  H04L25/0272 ,  H01L2924/00014

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US09916196B2

公开(公告)日：2018-03-13

申请号：US14631570

申请日：2015-02-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US09886993B2

公开(公告)日：2018-02-06

申请号：US15332785

申请日：2016-10-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US09851900B2

公开(公告)日：2017-12-26

申请号：US15629173

申请日：2017-06-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C8/12 ,  G06F12/06

CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1048 ,  G11C8/12 ,  G11C2207/107

Abstract: A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.

公开(公告)号：US20170351627A1

公开(公告)日：2017-12-07

申请号：US15533630

申请日：2015-10-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/287 ,  G06F13/16 ,  G06F2213/28 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20170337014A1

公开(公告)日：2017-11-23

申请号：US15522164

申请日：2015-11-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US20170330611A1

公开(公告)日：2017-11-16

申请号：US15610001

申请日：2017-05-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C29/52 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US09818463B2

公开(公告)日：2017-11-14

申请号：US15390681

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G06F12/00 ,  G11C8/18 ,  G11C7/10 ,  G06F13/16 ,  G06F13/42

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20170315953A1

公开(公告)日：2017-11-02

申请号：US15626038

申请日：2017-06-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F13/42

Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

公开(公告)号：US09785500B1

公开(公告)日：2017-10-10

申请号：US15390672

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz

IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/35

CPC classification number: G06F11/1048 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/356 ,  H03M13/6502

Abstract: A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.