公开(公告)号：US12120865B2

公开(公告)日：2024-10-15

申请号：US17132981

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

CPC classification number: H10B12/30 ,  H01L21/6835 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B53/30 ,  H01L2221/68363

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US12120545B2

公开(公告)日：2024-10-15

申请号：US17089588

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Ansab Ali ,  Sangeetha L. Bangolae ,  Youn Hyoung Heo

IPC: H04W28/02 ,  H04W4/40 ,  H04W28/04 ,  H04W80/02 ,  H04W88/02 ,  H04W92/18

CPC classification number: H04W28/0252 ,  H04W4/40 ,  H04W28/04 ,  H04W80/02 ,  H04W88/02 ,  H04W92/18

Abstract: Technologies and techniques associated with cross-layer quality of service (QOS) indication for sidelink communications are provided. In particular, mechanisms to handle priority and/or communication range requirements for medium access control (MAC) protocol data units (PDUs) with multiple logical channels (LCHs) are described. Other technologies and techniques may be described and/or claimed.

公开(公告)号：US12119344B2

公开(公告)日：2024-10-15

申请号：US17033440

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Anthony V. Mule' ,  David J. Towner ,  Dragos Seghete ,  Christopher R. Ryder ,  Angel Aquino Gonzalez

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/41791 ,  H01L29/785

Abstract: Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line.

公开(公告)号：US12119317B2

公开(公告)日：2024-10-15

申请号：US17032469

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Nagatoshi Tsunoda ,  Shawna M. Liff ,  Sairam Agraharam

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/0823 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

公开(公告)号：US12117960B2

公开(公告)日：2024-10-15

申请号：US17029288

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/4068 ,  G06F13/423

Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

公开(公告)号：US12117910B2

公开(公告)日：2024-10-15

申请号：US17868596

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Manasi Deval ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Alexander H. Duyck ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/20 ,  G06F3/06 ,  G06F9/455 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F11/2023 ,  G06F3/0622 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/45558 ,  G06F9/4856 ,  G06F11/2007 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/17331 ,  G06F2009/45562 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45595 ,  G06F2201/805 ,  G06F2201/815 ,  G06F2213/0026

Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.

公开(公告)号：US20240339412A1

公开(公告)日：2024-10-10

申请号：US18130584

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Cary KULIASHA ,  Brandon C. MARIN ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM

IPC: H01L23/538 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/645 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/1511

Abstract: Embodiments disclosed herein include an interconnect bridge. In an embodiment, the interconnect bridge comprises a substrate, and a first trace on the substrate. In an embodiment, a first layer is on the first trace, where the first layer comprises a magnetic material. In an embodiment, a second layer is over the substrate, where the second layer comprises an insulating material. In an embodiment, a second trace is embedded in the second layer.

公开(公告)号：US20240338789A1

公开(公告)日：2024-10-10

申请号：US18747926

申请日：2024-06-19

Applicant: Intel Corporation

Inventor： Songki Choi ,  Eunwoo Shin

IPC: G06T3/40 ,  G06T7/62

CPC classification number: G06T3/40 ,  G06T7/62

Abstract: Example apparatus disclosed herein determine an initial spatial input size for training a computer vision model, the initial spatial input size based on sizes of input training images, apply an adjustment to the initial spatial input size to determine an adjusted spatial input size, the adjustment based on sizes of objects in the input training images, and map the adjusted spatial input size to one of a set of available spatial input sizes to determine a final spatial input size for training the computer vision model. Some disclosed apparatus evaluates a linear model to determine a final batch size for training the computer vision model, the linear model based on first and second simulations of training the computer vision model, the first simulation based on the final spatial input size and a first batch size, the second simulation based on the final spatial input size and a second batch size.

公开(公告)号：US12114479B2

公开(公告)日：2024-10-08

申请号：US17368329

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H10B12/00 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/786

CPC classification number: H10B12/31 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L29/78696 ,  H10B12/30

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US12114355B2

公开(公告)日：2024-10-08

申请号：US18234697

申请日：2023-08-16

Applicant: Intel Corporation

Inventor： Yongjun Kwak ,  Lopamudra Kundu ,  Salvatore Talarico ,  Yingyang Li

IPC: H04W74/0808 ,  H04W16/14 ,  H04W72/0453 ,  H04W72/23 ,  H04W72/53 ,  H04W76/27

CPC classification number: H04W74/0808 ,  H04W16/14 ,  H04W72/0453 ,  H04W72/23 ,  H04W72/53 ,  H04W76/27

Abstract: Systems and methods for downlink transmission using a wideband unlicensed band carrier in 5G networks are described. The gNB determines, based on LBT, which LBT subchannel(s) in a BWP are available during a COT. The gNB transmits an indication of the available subchannels in DCI format 2_0 of a GC-PDCCH of one of the available subchannels and subsequently transmits a PDSCH using the available subchannel(s). The gNB may configure multiple opportunities during the COT and transmit the GC-PDCCH after the initial opportunity. The PDSCH is transmitted on all available subchannels during the COT and, during an initial portion of the COT, may transmit the PDSCH by puncturing symbols of the unavailable subchannels. The indication may include a bitmap of available subchannels or if the LBT outcome is not available, may indicate all or none of the subchannels or available or that the outcome is not available.