公开(公告)号：US20080258299A1

公开(公告)日：2008-10-23

申请号：US12073310

申请日：2008-03-04

Applicant: Un Byoung Kang ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

Inventor： Un Byoung Kang ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/83 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/01007 ,  H01L2924/01028 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成扩散阻挡层，并在衬底上形成至少两个特征，使得扩散阻挡层分别设置在每个特征和衬底之间，并接触至少两个特征。 衬底的第一杂质区包含第一类杂质，衬底的第二杂质区包含不同于第一类型的第二类杂质，所述至少两个特征的第一特征在第一杂质区， 并且所述至少两个特征的第二特征在于第二杂质区域，使得第二特征通过不同的杂质区域与第一特征电隔离。

公开(公告)号：US20080251872A1

公开(公告)日：2008-10-16

申请号：US11831768

申请日：2007-07-31

Applicant: Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

Inventor： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC: H01L27/12 ,  H01L21/02

CPC classification number: H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14685 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.

Abstract translation: 提供了图像传感器封装，其制造方法和包括图像传感器封装的图像传感器模块。 在图像传感器封装中，将图像传感器芯片安装在透光性基板的凹部上。 粘合剂将图像传感器芯片粘合到透射基板上，并将图像传感器芯片上的有源像素传感器（APS）密封并保护其免受细颗粒污染。 将IR切割膜设置在透射基底上以最小化图像传感器封装的高度。 图像传感器封装电连接到凹陷中的外部连接焊盘。 因此，图像传感器封装具有最小高度，不易受到颗粒污染，并且在制造期间不需要昂贵的对准过程。

公开(公告)号：US20080012084A1

公开(公告)日：2008-01-17

申请号：US11826124

申请日：2007-07-12

Applicant: Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

Inventor： Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC: H01L31/0232

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An image sensor package may include a transparent substrate, an image sensor chip having a sensing region disposed over the transparent substrate, a resin protection dam disposed between the image sensor chip and the transparent substrate inside a wiring pattern, the resin protection dam having an aperture formed to expose a sensing region of the image sensor chip and defining a cavity between the sensing region and the transparent substrate, a resin filled on the transparent substrate outside the resin protection dam, and a black matrix pattern disposed on each side of the transparent substrate and configured to block excess transmission of light.

Abstract translation: 图像传感器封装可以包括透明基板，具有设置在透明基板上的感测区域的图像传感器芯片，设置在图像传感器芯片和布线图案内的透明基板之间的树脂保护坝，树脂保护坝具有孔 形成为暴露图像传感器芯片的感测区域并且在感测区域和透明基板之间限定空腔，填充在树脂保护堤外的透明基板上的树脂和布置在透明基板的每一侧上的黑矩阵图案 并且被配置为阻止光的过量透射。

公开(公告)号：US20070152331A1

公开(公告)日：2007-07-05

申请号：US11513173

申请日：2006-08-31

Applicant: Uu-Byung Kang ,  Yong-Hwan Kwon ,  Jong-Ho Lee ,  Chung-Sun Lee

Inventor： Uu-Byung Kang ,  Yong-Hwan Kwon ,  Jong-Ho Lee ,  Chung-Sun Lee

IPC: H01L23/48

CPC classification number: C22C30/06 ,  B23K35/025 ,  B23K35/262 ,  B23K35/264 ,  B23K2101/40 ,  C22C12/00 ,  C22C13/00 ,  C22C13/02 ,  C22C30/02 ,  C22C30/04 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/3463 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Example embodiments of the present invention relate to an alloy solder and a semiconductor device using the alloy solder. Other example embodiments relate to an alloy solder capable of increasing reliability of a junction between a semiconductor chip and a substrate. According to still other example embodiments of the present invention, there may be a tin-bismuth (Sn—Bi) family alloy solder between a semiconductor chip and a substrate, and a semiconductor device using the alloy solder. The semiconductor device may include a semiconductor chip formed with a plurality of gold (Au) bumps, a substrate having metal wirings connected to the gold (Au) bumps, and a junction including a tin-bismuth (Sn—Bi) family alloy solder interposed between and connecting the gold (Au) bump and the metal wiring.The formation of a relatively large amount of AuSn4 intermetallic compound may be inhibited in the junction because gold (Au) may not easily diffuse into a tin-bismuth (Sn—Bi) family alloy solder of a liquid state during a reflow process for connecting the semiconductor chip and substrate. Therefore, most of the junction may be retained as the tin-bismuth (Sn—Bi) family alloy solder.

Abstract translation: 本发明的示例性实施例涉及合金焊料和使用该合金焊料的半导体器件。 其他示例实施例涉及能够增加半导体芯片和基板之间的结的可靠性的合金焊料。 根据本发明的另一个示例性实施例，可以在半导体芯片和衬底之间存在锡 - 铋（Sn-Bi）族合金焊料，以及使用该合金焊料的半导体器件。 半导体器件可以包括形成有多个金（Au）凸块的半导体芯片，具有连接到金（Au）凸块的金属布线的衬底以及插入了锡 - 铋（Sn-Bi）族合金焊料的接合部 之间并连接金（Au）凸块和金属布线。 由于金（Au）可能不容易扩散到液体的锡 - 铋（Sn-Bi）族合金焊料中，所以在结中可以抑制相对大量的AuSn 4+金属间化合物的形成 在用于连接半导体芯片和衬底的回流工艺期间状态。 因此，大部分接点可以作为锡 - 铋（Sn-Bi）族合金焊料保留。

公开(公告)号：US07190073B2

公开(公告)日：2007-03-13

申请号：US11158164

申请日：2005-06-20

Applicant: Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

Inventor： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

IPC: H01L23/48

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H05K3/0032 ,  H05K3/323 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A circuit film having film bumps is provided for a film package. An IC chip is mechanically joined and electrically coupled to the circuit film through the film bumps instead of conventional chip bumps. In a fabrication method, a base film is partially etched by a laser to create an etched area that defines raised portion relatively raised from the etched area. Then a circuit pattern is selectively formed on the base film, partly running over the raised portions. The raised portion and the overlying circuit pattern constitute the film bumps having a height not greater than the height of the circuit film.

Abstract translation: 为薄膜封装提供具有膜凸块的电路薄膜。 IC芯片通过膜凸块机械连接并电耦合到电路膜，而不是传统的芯片凸块。 在制造方法中，通过激光部分地蚀刻基底膜以产生限定从蚀刻区域相对升高的凸起部分的蚀刻区域。 然后，在基膜上选择性地形成电路图案，部分地在凸起部分上运行。 凸起部分和上覆电路图案构成具有不大于电路膜高度的高度的膜凸块。

公开(公告)号：US20060091504A1

公开(公告)日：2006-05-04

申请号：US11256650

申请日：2005-10-21

Applicant: Un-Byoung Kang ,  Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon

Inventor： Un-Byoung Kang ,  Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon

IPC: H01L23/58

CPC classification number: H05K3/3463 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13144 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/8181 ,  H01L2224/81825 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/189 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: In one embodiment, a film circuit substrate comprises an insulating film made of polyimide resin; a conductive circuit pattern formed on the insulating film, the circuit pattern including an inner lead to be connected with a conductive bump of a semiconductor chip through a bump bonding process; and a tin-indium alloy layer formed on the inner lead to produce an inter-metallic compound layer of AuxSn composition during the bump bonding process.

Abstract translation: 在一个实施例中，薄膜电路基板包括由聚酰亚胺树脂制成的绝缘膜; 形成在所述绝缘膜上的导电电路图案，所述电路图案包括通过凸块接合工艺与半导体芯片的导电凸块连接的内部引线; 以及形成在内部引线上的锡铟合金层，以在凸点焊接工艺期间产生Au / Sn组分的金属间化合物层。

公开(公告)号：US20050046033A1

公开(公告)日：2005-03-03

申请号：US10892360

申请日：2004-07-16

Applicant: Ye-Chung Chung ,  Chung-Sun Lee

Inventor： Ye-Chung Chung ,  Chung-Sun Lee

IPC: H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/36 ,  H01L23/48

CPC classification number: H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/112 ,  H05K3/361 ,  H01L2224/05599

Abstract: A tape circuit substrate and semiconductor chip package using the same. The tape circuit substrate may comprise a base film which may be made of an insulating material and may be formed with via-holes at portions thereof, a first wiring pattern layer which may be formed on a first surface of the base film, and at least one second wiring pattern layer which may be formed on a second surface of the base film and electrically connected to a terminal which may be formed on the first surface through conductive materials, or plugs, filled in the via-holes. The semiconductor chip package may comprise a semiconductor chip which may be electrically bonded to the tape circuit substrate through chip bumps.

Abstract translation: 带状电路基板和使用其的半导体芯片封装。 磁带电路基板可以包括可以由绝缘材料制成并且可以在其部分处形成有通孔的基膜，可以形成在基膜的第一表面上的第一布线图案层，并且至少 一个第二布线图案层可以形成在基膜的第二表面上并且电连接到可以通过填充在通孔中的导电材料或插塞形成在第一表面上的端子。 半导体芯片封装可以包括半导体芯片，其可以通过芯片凸块电连接到磁带电路基板。