公开(公告)号：US20080101045A1

公开(公告)日：2008-05-01

申请号：US11976070

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K1/18 ,  H05K3/20

CPC classification number: H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.

Abstract translation: 一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。 利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。

公开(公告)号：USD560180S1

公开(公告)日：2008-01-22

申请号：US29269991

申请日：2006-12-12

Applicant: Jung-Hyun Park ,  Min-Ho Cha ,  Hyun-Teak Lim

Designer： Jung-Hyun Park ,  Min-Ho Cha ,  Hyun-Teak Lim

公开(公告)号：US20080006942A1

公开(公告)日：2008-01-10

申请号：US11708568

申请日：2007-02-21

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bottom substrate of package on package and manufacturing method thereof is disclosed. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.

Abstract translation: 公开了一种封装的底部衬底及其制造方法。 封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体 层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量 安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是 可能在顶部基板和底部基板之间。

公开(公告)号：US20070281390A1

公开(公告)日：2007-12-06

申请号：US11727852

申请日：2007-03-28

Applicant: Myung-Sam Kang ,  Je-Gwang Yoo ,  Jung-Hyun Park ,  Ji-Eun Kim ,  Hoe-Ku Jung ,  Jin-Yong An

Inventor： Myung-Sam Kang ,  Je-Gwang Yoo ,  Jung-Hyun Park ,  Ji-Eun Kim ,  Hoe-Ku Jung ,  Jin-Yong An

IPC: H01L21/00

CPC classification number: H01L21/4846 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/064 ,  H05K3/108 ,  H05K3/242 ,  H05K3/243 ,  H05K3/427 ,  H05K2201/0376 ,  H05K2203/0361 ,  H05K2203/1394 ,  H01L2924/00

Abstract: The present invention relates to a manufacturing method of a package substrate. A manufacturing method of a package substrate for mounting an electric component by connecting electrodes of the electric component to bonding pads, includes: manufacturing a buried pattern substrate having a circuit pattern and bonding pads buried in an insulating layer and having a seed layer laminated on the insulating layer, laminating a dry film onto the seed layer and removing the seed layer and the dry film of the upper side of the bonding pads, performing surface-treatment using the remaining seed layer as a plating lead; and removing the remaining seed layer and the dry film such that the circuit pattern is exposed.

Abstract translation: 本发明涉及封装基板的制造方法。 一种用于通过将电气部件的电极连接到接合焊盘来安装电气部件的封装基板的制造方法，包括：制造具有电路图案的掩埋图案基板和埋在绝缘层中并具有层叠在所述绝缘层上的种子层的接合焊盘 绝缘层，将干膜层压到种子层上，去除接合焊盘的上侧的种子层和干膜，使用剩余的种子层作为电镀引线进行表面处理; 并且除去剩余的种子层和干膜，使得电路图案被暴露。

公开(公告)号：US20070210439A1

公开(公告)日：2007-09-13

申请号：US11715906

申请日：2007-03-09

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.

Abstract translation: 本发明的一个方面的特征在于片上封装的制造方法。 该方法可以包括：（a）在载体膜上层压干膜，其一面由薄金属膜层压; （b）通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; （c）去除干膜; （d）层压除了形成焊锡球焊盘的部分之外的上光阻焊剂; （e）蚀刻形成在上层光阻抗层未层叠的部分上的金属薄膜; （f）通过倒装芯片接合将半导体芯片安装在焊球垫上; （g）用钝化材料模制半导体芯片; （h）去除载体膜和金属薄膜; 和（i）在焊球垫下方层叠下光阻焊剂。 根据本发明的片上封装及其制造方法可以设计高密度电路，因为使用种子层形成电路图案。

公开(公告)号：USD530693S1

公开(公告)日：2006-10-24

申请号：US29237122

申请日：2005-08-26

Applicant: Jung-Hyun Park ,  Han Kim

Designer： Jung-Hyun Park ,  Han Kim

公开(公告)号：USD446198S1

公开(公告)日：2001-08-07

申请号：US29131937

申请日：2000-10-30

Applicant: Jung-Hyun Park ,  Jeong-Woo Kim ,  Myong-Ill Seo

Designer： Jung-Hyun Park ,  Jeong-Woo Kim ,  Myong-Ill Seo

公开(公告)号：US08973554B2

公开(公告)日：2015-03-10

申请号：US13642276

申请日：2010-10-26

Applicant: Deuk-Jin Park ,  Eung-Sung Kim ,  Ju-Tae Kim ,  Kang-Yun Jung ,  Kwang-Cheol Heo ,  Jong-Suk Kim ,  Jung-Hyun Park ,  Eun Ha ,  Beom-Yong No

Inventor： Deuk-Jin Park ,  Eung-Sung Kim ,  Ju-Tae Kim ,  Kang-Yun Jung ,  Kwang-Cheol Heo ,  Jong-Suk Kim ,  Jung-Hyun Park ,  Eun Ha ,  Beom-Yong No

IPC: F02M45/08 ,  F02M47/02 ,  F02M61/18 ,  F02M45/00

CPC classification number: F02M45/086 ,  F02M47/027 ,  F02M61/182 ,  F02M2200/46

Abstract: The present invention provides a two solenoid valve relay with a two-phase fuel injection valve for a diesel engine, which is installed on a valve itself to enable injection at pressure greater than opening pressure, at which the fuel enters into a fuel valve, thereby improving fuel injection performance, and which is configured to enable adjustment of an injection timing at the opening pressure within the valve, wherein injection timings through a solenoid valve is provided for low load and high load, respectively, such that a distinct difference exists between the injection timings to open the nozzle hole of the nozzle in a differential manner at pressure higher than the pressure, at which the fuel enters to the fuel valve and internal spring opening pressure, thereby injecting fuel at high pressure even at low load to facilitate vaporization, and wherein, in case of a high speed operation or high load, low pressure/high pressure needle valves are opened at the same time to quickly inject fuel of a high volume through a plurality of nozzle holes, thereby improving combustion performance of an engine, and wherein a space between the needle valve and the nozzle hole which are closed after the injection is minimized because the nozzle hole is opened differentially and sequentially according to pressure, thereby avoiding waste of fuel and reducing harmful gas (smoke, Nox).

Abstract translation: 本发明提供了一种具有用于柴油发动机的两相燃料喷射阀的两个电磁阀继电器，该电磁阀继电器安装在阀本身上以能够在大于开启压力的压力下喷射燃料进入燃料阀，由此 提高燃料喷射性能，并且其被配置为能够调节阀内的打开压力下的喷射正时，其中通过电磁阀分别为低负载和高负载提供喷射定时，使得在 喷射正时以不同于燃料进入燃料阀的压力和内部弹簧开启压力的压力以不同的方式打开喷嘴的喷嘴孔，从而甚至在低负载下高压喷射燃料以促进汽化， 并且其中，在高速运转或高负载的情况下，低压/高压针阀同时打开以快速地 通过多个喷嘴孔大体积的喷射燃料，从而改善发动机的燃烧性能，并且其中在喷射之后关闭的针阀和喷嘴孔之间的空间被最小化，因为喷嘴孔差异地并且顺序地打开 根据压力，从而避免燃料的浪费和减少有害气体（烟雾，Nox）。

公开(公告)号：USD687029S1

公开(公告)日：2013-07-30

申请号：US29422581

申请日：2012-05-22

Applicant: Jung-Hyun Park ,  Jae-Seung Song ,  Dong-Seok Lee

Designer： Jung-Hyun Park ,  Jae-Seung Song ,  Dong-Seok Lee

公开(公告)号：US08185055B2

公开(公告)日：2012-05-22

申请号：US12042521

申请日：2008-03-05

Applicant: Hyun Ho Choi ,  Hyo Sun Hwang ,  Tae In Hyon ,  Kyung Hun Jang ,  In Sun Lee ,  Hyun Gi Ahn ,  Yong Ho Cho ,  Dong Jo Park ,  Jung Hyun Park

Inventor： Hyun Ho Choi ,  Hyo Sun Hwang ,  Tae In Hyon ,  Kyung Hun Jang ,  In Sun Lee ,  Hyun Gi Ahn ,  Yong Ho Cho ,  Dong Jo Park ,  Jung Hyun Park

IPC: H04B1/00 ,  H04B15/00 ,  H04B17/00

CPC classification number: H04W16/14 ,  H04L27/2607 ,  H04L27/2647

Abstract: An interference determination apparatus, including a signal receiver to receive a first signal of a primary network and a second signal of a secondary network; a correlator to compute a correlation value of a first cyclic prefix included in the first signal and a correlation value of a second cyclic prefix included in the second signal; and an interference determination unit to determine an interference level or whether the interference occurs between the primary network and the secondary network, using the correlation value of the first cyclic prefix and the correlation value of the second cyclic prefix.

Abstract translation: 一种干扰确定装置，包括用于接收主网络的第一信号的信号接收器和辅助网络的第二信号; 相关器，用于计算包括在第一信号中的第一循环前缀的相关值和包括在第二信号中的第二循环前缀的相关值; 以及干扰确定单元，使用第一循环前缀的相关值和第二循环前缀的相关值来确定干扰电平或者是否在主网络和次网之间发生干扰。