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    BUFFERING DEVICE AND CONTROL METHOD THEREOF
    42.
    发明公开
    BUFFERING DEVICE AND CONTROL METHOD THEREOF 审中-公开

    公开(公告)号：US20240201895A1

    公开(公告)日：2024-06-20

    申请号：US18544144

    申请日：2023-12-18

    Applicant: Renesas Electronics Corporation

    Inventor： Kanta KUDO ,  Keiichiro SANO

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

    Abstract: By a buffering device, a first holding unit holds a write number value and a read number value for each of a plurality of grouping criteria. The grouping criteria include a priority of data units as one grouping parameter. A second holding unit holds a plurality of transmission commands. The plurality of transmission commands correspond to any of the plurality of grouping criteria. A control unit forms a “holding address” for causing the second holding unit to hold the written transmission commands in the second holding unit based on the write number value for the grouping criteria corresponding to the written transmission commands. The control unit forms an “output address” of the second holding unit, in which the read transmission commands are held, based on the information on the read number value for the grouping criteria corresponding to the read transmission commands.

    SEMICONDUCTOR DEVICE
    44.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240178317A1

    公开(公告)日：2024-05-30

    申请号：US18484956

    申请日：2023-10-11

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takahiro MORI

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7816 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681

    Abstract: In a p-type substrate region of a semiconductor substrate, an n-type source region, an n-type drain region, a p-type body region having an impurity concentration higher than an impurity concentration of the p-type substrate region, a p-type body contact region having an impurity concentration higher than the impurity concentration of the p-type body region, and an n-type drift region having an impurity concentration lower than an impurity concentration of the n-type drain region are formed. A gate electrode is formed on the semiconductor substrate via a gate dielectric film. The semiconductor substrate includes a first region and a second region that are alternately disposed in an extending direction of the gate electrode. A width of the p-type body region overlapping with the gate electrode in the second region is smaller than a width of the p-type body region overlapping with the gate electrode in the first region.

    CONNECTION CONTROL CIRCUIT, AND CONNECTION CONTROL METHOD
    45.
    发明公开
    CONNECTION CONTROL CIRCUIT, AND CONNECTION CONTROL METHOD 审中-公开

    公开(公告)号：US20240175943A1

    公开(公告)日：2024-05-30

    申请号：US18518327

    申请日：2023-11-22

    Applicant: Renesas Electronics Corporation

    Inventor： Takayuki SUZUKI

    IPC: G01R31/66 ,  G01R19/00 ,  H03K5/24

    CPC classification number: G01R31/66 ,  G01R19/0038 ,  H03K5/24

    Abstract: A connection control circuit according to an embodiment includes an operation mode detection circuit having an operation state control circuit. In a first state in which an other device is not connected to a first device, the operation state control circuit sets the receiver circuit to an operating state and the operation mode detection circuit to a stopped state. In addition, in a second state in which the other device is connected to the first device, the operation state control circuit sets the receiver circuit to a stopped state and the operation mode detection circuit to an operating state.

    SEMICONDUCTOR DEVICE
    47.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240170398A1

    公开(公告)日：2024-05-23

    申请号：US18511535

    申请日：2023-11-16

    Applicant: Renesas Electronics Corporation

    Inventor： Hiromichi TAKAOKA ,  Yoshiyuki SATO ,  Yuki FUJIMOTO

    IPC: H01L23/525

    CPC classification number: H01L23/5256

    Abstract: The dielectric film IF is disposed on the semiconductor substrate SB, and the plurality of electric fuse portions FU are disposed on the dielectric film IF. The n-type first well region WL1 is disposed in the semiconductor substrate SB and on the surface of the semiconductor substrate SB. The first well region WL1 is formed by integrally connecting the well region WLa located under each of the plurality of electric fuse portions FU to each other.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    48.
    发明公开
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240170346A1

    公开(公告)日：2024-05-23

    申请号：US18452822

    申请日：2023-08-21

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kosuke KITAICHI

    IPC: H01L21/66 ,  H01L21/78 ,  H01L29/40 ,  H01L29/66

    CPC classification number: H01L22/14 ,  H01L21/78 ,  H01L29/402 ,  H01L29/66348

    Abstract: In a wafer test step, a dummy semiconductor element formed in a scribe region of a semiconductor substrate is inspected by using a testing electrode provided in the scribe region and electrically connected to the dummy semiconductor element. In a dicing step, the scribe region of the semiconductor substrate is cut by using a dicing blade. The testing electrode includes a plurality of pad portions and a plurality of connection portions connecting the plurality of pad portions to each other. A width of each of the plurality of connection portions is larger than a width of the dicing blade, and smaller than a width of each of the plurality of pad portions. In plan view, the plurality of pad portions is arranged in a linear manner in a moving direction of the dicing blade, and the plurality of connection portions is arranged in a staggered manner in the moving direction.

    COMMUNICATION DEVICE, RELEASE METHOD OF BUFFER, AND PROGRAM
    49.
    发明公开
    COMMUNICATION DEVICE, RELEASE METHOD OF BUFFER, AND PROGRAM 审中-公开

    公开(公告)号：US20240168908A1

    公开(公告)日：2024-05-23

    申请号：US18483711

    申请日：2023-10-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Tomoyuki NAKAMURA

    IPC: G06F13/42 ,  G06F9/54

    CPC classification number: G06F13/42 ,  G06F9/54

    Abstract: A communication device includes at least one memory and at least one processor coupled to the at least one memory. The at least one processor is configured to: secure a transmission buffer that is not optionally released by a user application; monitor a storage area in which a specific field in an upper protocol header included in payload data of a frame transmitted from the transmission buffer is written; and release the transmission buffer in a case where a storage value stored in the storage area has not been updated for a certain period of time.

    Semiconductor device having conductive patterns with mesh pattern and differential signal wirings
    50.
    发明授权
    Semiconductor device having conductive patterns with mesh pattern and differential signal wirings 有权

    公开(公告)号：US11990397B2

    公开(公告)日：2024-05-21

    申请号：US18163617

    申请日：2023-02-02

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Wataru Shiroi ,  Shuuichi Kariyazaki

    IPC: H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/15

    Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

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